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619 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __sparc64_MMU_H__
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#define __sparc64_MMU_H__
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <arch/types.h>
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#include <typedefs.h>
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/** LSU Control Register ASI. */
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#define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
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/** I-MMU ASIs. */
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#define ASI_IMMU            0x50
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#define ASI_IMMU_TSB_8KB_PTR_REG    0x51    
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#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
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#define ASI_ITLB_DATA_IN_REG        0x54
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#define ASI_ITLB_DATA_ACCESS_REG    0x55
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#define ASI_ITLB_TAG_READ_REG       0x56
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#define ASI_IMMU_DEMAP          0x57
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/** Virtual Addresses within ASI_IMMU. */
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#define VA_IMMU_TAG_TARGET      0x0 /**< IMMU tag target register. */
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#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
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#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
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#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
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/** D-MMU ASIs. */
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#define ASI_DMMU            0x58
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#define ASI_DMMU_TSB_8KB_PTR_REG    0x59    
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#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
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#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
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#define ASI_DTLB_DATA_IN_REG        0x5c
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#define ASI_DTLB_DATA_ACCESS_REG    0x5d
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#define ASI_DTLB_TAG_READ_REG       0x5e
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#define ASI_DMMU_DEMAP          0x5f
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/** Virtual Addresses within ASI_DMMU. */
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#define VA_DMMU_TAG_TARGET      0x0 /**< DMMU tag target register. */
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#define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
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#define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
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#define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
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#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
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#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
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#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
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#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
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#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
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/** LSU Control Register. */
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union lsu_cr_reg {
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    __u64 value;
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    struct {
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        unsigned : 23;
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        unsigned pm : 8;
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        unsigned vm : 8;
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        unsigned pr : 1;
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        unsigned pw : 1;
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        unsigned vr : 1;
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        unsigned vw : 1;
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        unsigned : 1;
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        unsigned fm : 16;  
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        unsigned dm : 1;    /**< D-MMU enable. */
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        unsigned im : 1;    /**< I-MMU enable. */
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        unsigned dc : 1;    /**< D-Cache enable. */
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        unsigned ic : 1;    /**< I-Cache enable. */
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    } __attribute__ ((packed));
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};
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typedef union lsu_cr_reg lsu_cr_reg_t;
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#define immu_enable()   immu_set(true)
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#define immu_disable()  immu_set(false)
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#define dmmu_enable()   dmmu_set(true)
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#define dmmu_disable()  dmmu_set(false)
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/** Disable or Enable IMMU. */
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static inline immu_set(bool enable)
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{
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    lsu_cr_reg_t cr;
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    cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
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    cr.im = enable;
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    asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
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    flush();
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}
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/** Disable or Enable DMMU. */
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static inline dmmu_set(bool enable)
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{
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    lsu_cr_reg_t cr;
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    cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
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    cr.dm = enable;
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    asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
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    flush();
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}
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#endif