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178 palkovsky 1
/*
2071 jermar 2
 * Copyright (c) 2001-2004 Jakub Jermar
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 * Copyright (c) 2005-2006 Ondrej Palkovsky
178 palkovsky 4
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1888 jermar 30
/** @addtogroup amd64  
1702 cejka 31
 * @{
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 */
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/** @file
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 */
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2227 decky 36
#include <arch.h>
178 palkovsky 37
#include <arch/pm.h>
206 palkovsky 38
#include <arch/asm.h>
1252 palkovsky 39
#include <mm/as.h>
2089 decky 40
#include <mm/frame.h>
206 palkovsky 41
#include <memstr.h>
814 palkovsky 42
#include <mm/slab.h>
206 palkovsky 43
 
178 palkovsky 44
/*
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 * There is no segmentation in long mode so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 */
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1187 jermar 50
descriptor_t gdt[GDT_ITEMS] = {
178 palkovsky 51
    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
188 palkovsky 57
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
178 palkovsky 58
      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 1,
188 palkovsky 61
      .special     = 0,
178 palkovsky 62
      .granularity = 1,
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      .base_24_31  = 0 },
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    /* KDATA descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 0,
188 palkovsky 73
      .granularity = 1,
178 palkovsky 74
      .base_24_31  = 0 },
803 palkovsky 75
    /* UDATA descriptor */
178 palkovsky 76
    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
803 palkovsky 79
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
178 palkovsky 80
      .limit_16_19 = 0xf,
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      .available   = 0,
803 palkovsky 82
      .longmode    = 0,
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      .special     = 1,
206 palkovsky 84
      .granularity = 1,
178 palkovsky 85
      .base_24_31  = 0 },
803 palkovsky 86
    /* UTEXT descriptor */
178 palkovsky 87
    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
803 palkovsky 90
      .access      = AR_PRESENT | AR_CODE | DPL_USER,
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      .limit_16_19 = 0xf,
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      .available   = 0,
803 palkovsky 93
      .longmode    = 1,
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      .special     = 0,
178 palkovsky 95
      .granularity = 1,
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      .base_24_31  = 0 },
332 palkovsky 97
    /* KTEXT 32-bit protected, for protected mode before long mode */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
277 palkovsky 105
      .special     = 1,
188 palkovsky 106
      .granularity = 1,
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      .base_24_31  = 0 },
206 palkovsky 108
    /* TSS descriptor - set up will be completed later,
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     * on AMD64 it is 64-bit - 2 items in table */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1289 vana 111
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* VESA Init descriptor */
1292 vana 113
#ifdef CONFIG_FB    
1289 vana 114
    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
1292 vana 115
#endif
178 palkovsky 116
};
117
 
1187 jermar 118
idescriptor_t idt[IDT_ITEMS];
178 palkovsky 119
 
1780 jermar 120
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt };
121
ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt };
229 palkovsky 122
 
1187 jermar 123
static tss_t tss;
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tss_t *tss_p = NULL;
178 palkovsky 125
 
1780 jermar 126
void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
206 palkovsky 127
{
1187 jermar 128
    tss_descriptor_t *td = (tss_descriptor_t *) d;
206 palkovsky 129
 
130
    td->base_0_15 = base & 0xffff;
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    td->base_16_23 = ((base) >> 16) & 0xff;
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    td->base_24_31 = ((base) >> 24) & 0xff;
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    td->base_32_63 = ((base) >> 32);
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}
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1780 jermar 136
void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
206 palkovsky 137
{
1187 jermar 138
    struct tss_descriptor *td = (tss_descriptor_t *) d;
206 palkovsky 139
 
140
    td->limit_0_15 = limit & 0xffff;
141
    td->limit_16_19 = (limit >> 16) & 0xf;
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}
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1780 jermar 144
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
206 palkovsky 145
{
146
    /*
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     * Offset is a linear address.
148
     */
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    d->offset_0_15 = offset & 0xffff;
150
    d->offset_16_31 = offset >> 16 & 0xffff;
151
    d->offset_32_63 = offset >> 32;
152
}
153
 
1187 jermar 154
void tss_initialize(tss_t *t)
206 palkovsky 155
{
1780 jermar 156
    memsetb((uintptr_t) t, sizeof(tss_t), 0);
206 palkovsky 157
}
158
 
159
/*
160
 * This function takes care of proper setup of IDT and IDTR.
161
 */
162
void idt_init(void)
163
{
1187 jermar 164
    idescriptor_t *d;
206 palkovsky 165
    int i;
166
 
167
    for (i = 0; i < IDT_ITEMS; i++) {
168
        d = &idt[i];
169
 
170
        d->unused = 0;
211 palkovsky 171
        d->selector = gdtselector(KTEXT_DES);
206 palkovsky 172
 
173
        d->present = 1;
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        d->type = AR_INTERRUPT; /* masking interrupt */
175
 
1780 jermar 176
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
206 palkovsky 177
    }
178
}
179
 
799 palkovsky 180
/** Initialize segmentation - code/data/idt tables
181
 *
182
 */
206 palkovsky 183
void pm_init(void)
184
{
1187 jermar 185
    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
186
    tss_descriptor_t *tss_desc;
206 palkovsky 187
 
188
    /*
189
     * Each CPU has its private GDT and TSS.
190
     * All CPUs share one IDT.
191
     */
192
 
193
    if (config.cpu_active == 1) {
194
        idt_init();
195
        /*
196
         * NOTE: bootstrap CPU has statically allocated TSS, because
197
         * the heap hasn't been initialized so far.
198
         */
199
        tss_p = &tss;
200
    }
201
    else {
1252 palkovsky 202
        /* We are going to use malloc, which may return
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         * non boot-mapped pointer, initialize the CR3 register
204
         * ahead of page_init */
2106 jermar 205
        write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
1252 palkovsky 206
 
1187 jermar 207
        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
206 palkovsky 208
        if (!tss_p)
209
            panic("could not allocate TSS\n");
210
    }
211
 
212
    tss_initialize(tss_p);
213
 
1187 jermar 214
    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
208 palkovsky 215
    tss_desc->present = 1;
216
    tss_desc->type = AR_TSS;
217
    tss_desc->dpl = PL_KERNEL;
206 palkovsky 218
 
1780 jermar 219
    gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
1251 jermar 220
    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
206 palkovsky 221
 
1186 jermar 222
    gdtr_load(&gdtr);
223
    idtr_load(&idtr);
206 palkovsky 224
    /*
225
     * As of this moment, the current CPU has its own GDT pointing
226
     * to its own TSS. We just need to load the TR register.
227
     */
1186 jermar 228
    tr_load(gdtselector(TSS_DES));
206 palkovsky 229
}
1702 cejka 230
 
2227 decky 231
/* Reboot the machine by initiating
232
 * a triple fault
233
 */
234
void arch_reboot(void)
235
{
236
    preemption_disable();
237
    ipl_t ipl = interrupts_disable();
238
 
239
    memsetb((uintptr_t) idt, sizeof(idt), 0);
240
    idtr_load(&idtr);
241
 
242
    interrupts_restore(ipl);
243
    asm volatile (
244
        "int $0x03\n"
2233 decky 245
        "cli\n"
2227 decky 246
        "hlt\n"
247
    );
248
}
249
 
1888 jermar 250
/** @}
1702 cejka 251
 */