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570 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
570 jermar 3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
1792 jermar 29
/** @addtogroup sparc64mm  
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
570 jermar 35
#include <arch/mm/tlb.h>
36
#include <mm/tlb.h>
1851 jermar 37
#include <mm/as.h>
38
#include <mm/asid.h>
619 jermar 39
#include <arch/mm/frame.h>
40
#include <arch/mm/page.h>
41
#include <arch/mm/mmu.h>
1851 jermar 42
#include <arch/interrupt.h>
1870 jermar 43
#include <interrupt.h>
1851 jermar 44
#include <arch.h>
570 jermar 45
#include <print.h>
617 jermar 46
#include <arch/types.h>
619 jermar 47
#include <config.h>
630 jermar 48
#include <arch/trap/trap.h>
1880 jermar 49
#include <arch/trap/exception.h>
863 jermar 50
#include <panic.h>
873 jermar 51
#include <arch/asm.h>
894 jermar 52
 
1891 jermar 53
#ifdef CONFIG_TSB
54
#include <arch/mm/tsb.h>
55
#endif
56
 
4055 trochtova 57
static void dtlb_pte_copy(pte_t *, index_t, bool);
58
static void itlb_pte_copy(pte_t *, index_t);
59
static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
60
static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
61
    const char *);
62
static void do_fast_data_access_protection_fault(istate_t *,
63
    tlb_tag_access_reg_t, const char *);
1851 jermar 64
 
873 jermar 65
char *context_encoding[] = {
66
    "Primary",
67
    "Secondary",
68
    "Nucleus",
69
    "Reserved"
70
};
71
 
570 jermar 72
void tlb_arch_init(void)
73
{
1793 jermar 74
    /*
1905 jermar 75
     * Invalidate all non-locked DTLB and ITLB entries.
1793 jermar 76
     */
1905 jermar 77
    tlb_invalidate_all();
1946 jermar 78
 
79
    /*
80
     * Clear both SFSRs.
81
     */
82
    dtlb_sfsr_write(0);
83
    itlb_sfsr_write(0);
897 jermar 84
}
873 jermar 85
 
897 jermar 86
/** Insert privileged mapping into DMMU TLB.
87
 *
4055 trochtova 88
 * @param page      Virtual page address.
89
 * @param frame     Physical frame address.
90
 * @param pagesize  Page size.
91
 * @param locked    True for permanent mappings, false otherwise.
92
 * @param cacheable True if the mapping is cacheable, false otherwise.
897 jermar 93
 */
2141 jermar 94
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
95
    bool locked, bool cacheable)
897 jermar 96
{
97
    tlb_tag_access_reg_t tag;
98
    tlb_data_t data;
99
    page_address_t pg;
100
    frame_address_t fr;
873 jermar 101
 
897 jermar 102
    pg.address = page;
103
    fr.address = frame;
873 jermar 104
 
4055 trochtova 105
    tag.context = ASID_KERNEL;
894 jermar 106
    tag.vpn = pg.vpn;
107
 
108
    dtlb_tag_access_write(tag.value);
109
 
110
    data.value = 0;
111
    data.v = true;
897 jermar 112
    data.size = pagesize;
894 jermar 113
    data.pfn = fr.pfn;
897 jermar 114
    data.l = locked;
115
    data.cp = cacheable;
2009 jermar 116
#ifdef CONFIG_VIRT_IDX_DCACHE
897 jermar 117
    data.cv = cacheable;
2009 jermar 118
#endif /* CONFIG_VIRT_IDX_DCACHE */
894 jermar 119
    data.p = true;
120
    data.w = true;
1868 jermar 121
    data.g = false;
894 jermar 122
 
123
    dtlb_data_in_write(data.value);
570 jermar 124
}
125
 
1852 jermar 126
/** Copy PTE to TLB.
127
 *
4055 trochtova 128
 * @param t         Page Table Entry to be copied.
129
 * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
130
 * @param ro        If true, the entry will be created read-only, regardless
131
 *          of its w field.
1852 jermar 132
 */
2141 jermar 133
void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
1851 jermar 134
{
1852 jermar 135
    tlb_tag_access_reg_t tag;
136
    tlb_data_t data;
137
    page_address_t pg;
138
    frame_address_t fr;
139
 
2141 jermar 140
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
141
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
1852 jermar 142
 
143
    tag.value = 0;
144
    tag.context = t->as->asid;
145
    tag.vpn = pg.vpn;
2141 jermar 146
 
1852 jermar 147
    dtlb_tag_access_write(tag.value);
2141 jermar 148
 
1852 jermar 149
    data.value = 0;
150
    data.v = true;
151
    data.size = PAGESIZE_8K;
152
    data.pfn = fr.pfn;
153
    data.l = false;
154
    data.cp = t->c;
2009 jermar 155
#ifdef CONFIG_VIRT_IDX_DCACHE
1852 jermar 156
    data.cv = t->c;
2009 jermar 157
#endif /* CONFIG_VIRT_IDX_DCACHE */
1864 jermar 158
    data.p = t->k;      /* p like privileged */
1852 jermar 159
    data.w = ro ? false : t->w;
160
    data.g = t->g;
2141 jermar 161
 
1852 jermar 162
    dtlb_data_in_write(data.value);
1851 jermar 163
}
164
 
1891 jermar 165
/** Copy PTE to ITLB.
166
 *
4055 trochtova 167
 * @param t     Page Table Entry to be copied.
168
 * @param index     Zero if lower 8K-subpage, one if higher 8K-subpage.
1891 jermar 169
 */
2141 jermar 170
void itlb_pte_copy(pte_t *t, index_t index)
1852 jermar 171
{
172
    tlb_tag_access_reg_t tag;
173
    tlb_data_t data;
174
    page_address_t pg;
175
    frame_address_t fr;
176
 
2141 jermar 177
    pg.address = t->page + (index << MMU_PAGE_WIDTH);
178
    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
1852 jermar 179
 
180
    tag.value = 0;
181
    tag.context = t->as->asid;
182
    tag.vpn = pg.vpn;
183
 
184
    itlb_tag_access_write(tag.value);
185
 
186
    data.value = 0;
187
    data.v = true;
188
    data.size = PAGESIZE_8K;
189
    data.pfn = fr.pfn;
190
    data.l = false;
191
    data.cp = t->c;
1864 jermar 192
    data.p = t->k;      /* p like privileged */
1852 jermar 193
    data.w = false;
194
    data.g = t->g;
195
 
196
    itlb_data_in_write(data.value);
197
}
198
 
863 jermar 199
/** ITLB miss handler. */
2231 jermar 200
void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
863 jermar 201
{
4296 trochtova 202
    uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
2141 jermar 203
    index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
1852 jermar 204
    pte_t *t;
205
 
206
    page_table_lock(AS, true);
4296 trochtova 207
    t = page_mapping_find(AS, page_16k);
1852 jermar 208
    if (t && PTE_EXECUTABLE(t)) {
209
        /*
210
         * The mapping was found in the software page hash table.
211
         * Insert it into ITLB.
212
         */
213
        t->a = true;
2141 jermar 214
        itlb_pte_copy(t, index);
1891 jermar 215
#ifdef CONFIG_TSB
2141 jermar 216
        itsb_pte_copy(t, index);
1891 jermar 217
#endif
1852 jermar 218
        page_table_unlock(AS, true);
219
    } else {
220
        /*
2048 jermar 221
         * Forward the page fault to the address space page fault
222
         * handler.
1852 jermar 223
         */    
224
        page_table_unlock(AS, true);
4296 trochtova 225
        if (as_page_fault(page_16k, PF_ACCESS_EXEC, istate) ==
226
            AS_PF_FAULT) {
2048 jermar 227
            do_fast_instruction_access_mmu_miss_fault(istate,
2462 jermar 228
                __func__);
1852 jermar 229
        }
230
    }
863 jermar 231
}
232
 
1851 jermar 233
/** DTLB miss handler.
234
 *
2048 jermar 235
 * Note that some faults (e.g. kernel faults) were already resolved by the
236
 * low-level, assembly language part of the fast_data_access_mmu_miss handler.
2231 jermar 237
 *
4055 trochtova 238
 * @param tag       Content of the TLB Tag Access register as it existed
239
 *          when the trap happened. This is to prevent confusion
240
 *          created by clobbered Tag Access register during a nested
241
 *          DTLB miss.
242
 * @param istate    Interrupted state saved on the stack.
1851 jermar 243
 */
2231 jermar 244
void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
863 jermar 245
{
4296 trochtova 246
    uintptr_t page_8k;
247
    uintptr_t page_16k;
2141 jermar 248
    index_t index;
1851 jermar 249
    pte_t *t;
883 jermar 250
 
4296 trochtova 251
    page_8k = (uint64_t) tag.vpn << MMU_PAGE_WIDTH;
252
    page_16k = ALIGN_DOWN(page_8k, PAGE_SIZE);
2141 jermar 253
    index = tag.vpn % MMU_PAGES_PER_PAGE;
1865 jermar 254
 
1851 jermar 255
    if (tag.context == ASID_KERNEL) {
256
        if (!tag.vpn) {
257
            /* NULL access in kernel */
2048 jermar 258
            do_fast_data_access_mmu_miss_fault(istate, tag,
2462 jermar 259
                __func__);
4296 trochtova 260
        } else if (page_8k >= end_of_identity) {
261
            /*
262
             * The kernel is accessing the I/O space.
263
             * We still do identity mapping for I/O,
264
             * but without caching.
265
             */
266
            dtlb_insert_mapping(page_8k, KA2PA(page_8k),
267
                PAGESIZE_8K, false, false);
268
            return;
1851 jermar 269
        }
2048 jermar 270
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
2141 jermar 271
            "kernel page fault.");
1851 jermar 272
    }
873 jermar 273
 
1851 jermar 274
    page_table_lock(AS, true);
4296 trochtova 275
    t = page_mapping_find(AS, page_16k);
1851 jermar 276
    if (t) {
277
        /*
278
         * The mapping was found in the software page hash table.
279
         * Insert it into DTLB.
280
         */
1852 jermar 281
        t->a = true;
2141 jermar 282
        dtlb_pte_copy(t, index, true);
1891 jermar 283
#ifdef CONFIG_TSB
2141 jermar 284
        dtsb_pte_copy(t, index, true);
1891 jermar 285
#endif
1851 jermar 286
        page_table_unlock(AS, true);
287
    } else {
288
        /*
2141 jermar 289
         * Forward the page fault to the address space page fault
290
         * handler.
1851 jermar 291
         */    
292
        page_table_unlock(AS, true);
4296 trochtova 293
        if (as_page_fault(page_16k, PF_ACCESS_READ, istate) ==
294
            AS_PF_FAULT) {
2048 jermar 295
            do_fast_data_access_mmu_miss_fault(istate, tag,
2462 jermar 296
                __func__);
1851 jermar 297
        }
877 jermar 298
    }
863 jermar 299
}
300
 
2231 jermar 301
/** DTLB protection fault handler.
302
 *
4055 trochtova 303
 * @param tag       Content of the TLB Tag Access register as it existed
304
 *          when the trap happened. This is to prevent confusion
305
 *          created by clobbered Tag Access register during a nested
306
 *          DTLB miss.
307
 * @param istate    Interrupted state saved on the stack.
2231 jermar 308
 */
309
void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
863 jermar 310
{
4296 trochtova 311
    uintptr_t page_16k;
2141 jermar 312
    index_t index;
1859 jermar 313
    pte_t *t;
314
 
4296 trochtova 315
    page_16k = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
2141 jermar 316
    index = tag.vpn % MMU_PAGES_PER_PAGE;   /* 16K-page emulation */
1859 jermar 317
 
318
    page_table_lock(AS, true);
4296 trochtova 319
    t = page_mapping_find(AS, page_16k);
1859 jermar 320
    if (t && PTE_WRITABLE(t)) {
321
        /*
2048 jermar 322
         * The mapping was found in the software page hash table and is
323
         * writable. Demap the old mapping and insert an updated mapping
324
         * into DTLB.
1859 jermar 325
         */
326
        t->a = true;
327
        t->d = true;
2141 jermar 328
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
4296 trochtova 329
            page_16k + index * MMU_PAGE_SIZE);
2141 jermar 330
        dtlb_pte_copy(t, index, false);
1891 jermar 331
#ifdef CONFIG_TSB
2141 jermar 332
        dtsb_pte_copy(t, index, false);
1891 jermar 333
#endif
1859 jermar 334
        page_table_unlock(AS, true);
335
    } else {
336
        /*
2048 jermar 337
         * Forward the page fault to the address space page fault
338
         * handler.
1859 jermar 339
         */    
340
        page_table_unlock(AS, true);
4296 trochtova 341
        if (as_page_fault(page_16k, PF_ACCESS_WRITE, istate) ==
342
            AS_PF_FAULT) {
2048 jermar 343
            do_fast_data_access_protection_fault(istate, tag,
2462 jermar 344
                __func__);
1859 jermar 345
        }
346
    }
863 jermar 347
}
348
 
4055 trochtova 349
/** Print TLB entry (for debugging purposes).
350
 *
351
 * The diag field has been left out in order to make this function more generic
352
 * (there is no diag field in US3 architeture).
353
 *
354
 * @param i     TLB entry number
355
 * @param t     TLB entry tag
356
 * @param d     TLB entry data
357
 */
358
static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
359
{
360
    printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
361
        "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, "
362
        "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
363
        t.context, d.v, d.size, d.nfo, d.ie, d.soft2,
364
        d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
365
}
366
 
367
#if defined (US)
368
 
570 jermar 369
/** Print contents of both TLBs. */
370
void tlb_print(void)
371
{
372
    int i;
373
    tlb_data_t d;
374
    tlb_tag_read_reg_t t;
375
 
376
    printf("I-TLB contents:\n");
377
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
378
        d.value = itlb_data_access_read(i);
613 jermar 379
        t.value = itlb_tag_read_read(i);
4055 trochtova 380
        print_tlb_entry(i, t, d);
570 jermar 381
    }
382
 
383
    printf("D-TLB contents:\n");
384
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
385
        d.value = dtlb_data_access_read(i);
613 jermar 386
        t.value = dtlb_tag_read_read(i);
4055 trochtova 387
        print_tlb_entry(i, t, d);
570 jermar 388
    }
4055 trochtova 389
}
570 jermar 390
 
4055 trochtova 391
#elif defined (US3)
392
 
393
/** Print contents of all TLBs. */
394
void tlb_print(void)
395
{
396
    int i;
397
    tlb_data_t d;
398
    tlb_tag_read_reg_t t;
399
 
400
    printf("TLB_ISMALL contents:\n");
401
    for (i = 0; i < tlb_ismall_size(); i++) {
402
        d.value = dtlb_data_access_read(TLB_ISMALL, i);
403
        t.value = dtlb_tag_read_read(TLB_ISMALL, i);
404
        print_tlb_entry(i, t, d);
405
    }
406
 
407
    printf("TLB_IBIG contents:\n");
408
    for (i = 0; i < tlb_ibig_size(); i++) {
409
        d.value = dtlb_data_access_read(TLB_IBIG, i);
410
        t.value = dtlb_tag_read_read(TLB_IBIG, i);
411
        print_tlb_entry(i, t, d);
412
    }
413
 
414
    printf("TLB_DSMALL contents:\n");
415
    for (i = 0; i < tlb_dsmall_size(); i++) {
416
        d.value = dtlb_data_access_read(TLB_DSMALL, i);
417
        t.value = dtlb_tag_read_read(TLB_DSMALL, i);
418
        print_tlb_entry(i, t, d);
419
    }
420
 
421
    printf("TLB_DBIG_1 contents:\n");
422
    for (i = 0; i < tlb_dbig_size(); i++) {
423
        d.value = dtlb_data_access_read(TLB_DBIG_0, i);
424
        t.value = dtlb_tag_read_read(TLB_DBIG_0, i);
425
        print_tlb_entry(i, t, d);
426
    }
427
 
428
    printf("TLB_DBIG_2 contents:\n");
429
    for (i = 0; i < tlb_dbig_size(); i++) {
430
        d.value = dtlb_data_access_read(TLB_DBIG_1, i);
431
        t.value = dtlb_tag_read_read(TLB_DBIG_1, i);
432
        print_tlb_entry(i, t, d);
433
    }
570 jermar 434
}
617 jermar 435
 
4055 trochtova 436
#endif
437
 
2141 jermar 438
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
439
    const char *str)
1852 jermar 440
{
4055 trochtova 441
    fault_if_from_uspace(istate, "%s.", str);
1880 jermar 442
    dump_istate(istate);
4055 trochtova 443
    panic("%s.", str);
1852 jermar 444
}
445
 
2141 jermar 446
void do_fast_data_access_mmu_miss_fault(istate_t *istate,
447
    tlb_tag_access_reg_t tag, const char *str)
1851 jermar 448
{
449
    uintptr_t va;
450
 
2141 jermar 451
    va = tag.vpn << MMU_PAGE_WIDTH;
2231 jermar 452
    if (tag.context) {
4055 trochtova 453
        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
2231 jermar 454
            tag.context);
455
    }
1880 jermar 456
    dump_istate(istate);
4055 trochtova 457
    printf("Faulting page: %p, ASID=%d.\n", va, tag.context);
458
    panic("%s.", str);
1851 jermar 459
}
460
 
2141 jermar 461
void do_fast_data_access_protection_fault(istate_t *istate,
462
    tlb_tag_access_reg_t tag, const char *str)
1859 jermar 463
{
464
    uintptr_t va;
465
 
2141 jermar 466
    va = tag.vpn << MMU_PAGE_WIDTH;
1859 jermar 467
 
2231 jermar 468
    if (tag.context) {
4055 trochtova 469
        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va,
2231 jermar 470
            tag.context);
471
    }
1859 jermar 472
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
1880 jermar 473
    dump_istate(istate);
4055 trochtova 474
    panic("%s.", str);
1859 jermar 475
}
476
 
1946 jermar 477
void dump_sfsr_and_sfar(void)
478
{
479
    tlb_sfsr_reg_t sfsr;
480
    uintptr_t sfar;
481
 
482
    sfsr.value = dtlb_sfsr_read();
483
    sfar = dtlb_sfar_read();
484
 
4055 trochtova 485
#if defined (US)
2048 jermar 486
    printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
2141 jermar 487
        "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
488
        sfsr.ow, sfsr.fv);
4055 trochtova 489
#elif defined (US3)
490
    printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, "
491
        "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft,
492
        sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
493
#endif
494
 
1946 jermar 495
    printf("DTLB SFAR: address=%p\n", sfar);
496
 
497
    dtlb_sfsr_write(0);
498
}
499
 
4420 trochtova 500
#if defined (US)
617 jermar 501
/** Invalidate all unlocked ITLB and DTLB entries. */
502
void tlb_invalidate_all(void)
503
{
504
    int i;
4055 trochtova 505
 
2078 jermar 506
    /*
507
     * Walk all ITLB and DTLB entries and remove all unlocked mappings.
508
     *
509
     * The kernel doesn't use global mappings so any locked global mappings
4055 trochtova 510
     * found must have been created by someone else. Their only purpose now
2078 jermar 511
     * is to collide with proper mappings. Invalidate immediately. It should
512
     * be safe to invalidate them as late as now.
513
     */
514
 
4055 trochtova 515
    tlb_data_t d;
516
    tlb_tag_read_reg_t t;
517
 
617 jermar 518
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
519
        d.value = itlb_data_access_read(i);
2078 jermar 520
        if (!d.l || d.g) {
617 jermar 521
            t.value = itlb_tag_read_read(i);
522
            d.v = false;
523
            itlb_tag_access_write(t.value);
524
            itlb_data_access_write(i, d.value);
525
        }
526
    }
4055 trochtova 527
 
617 jermar 528
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
529
        d.value = dtlb_data_access_read(i);
2078 jermar 530
        if (!d.l || d.g) {
617 jermar 531
            t.value = dtlb_tag_read_read(i);
532
            d.v = false;
533
            dtlb_tag_access_write(t.value);
534
            dtlb_data_access_write(i, d.value);
535
        }
536
    }
4055 trochtova 537
 
4420 trochtova 538
}
539
 
4055 trochtova 540
#elif defined (US3)
541
 
4420 trochtova 542
/** Invalidate all unlocked ITLB and DTLB entries. */
543
void tlb_invalidate_all(void)
544
{
545
    itlb_demap(TLB_DEMAP_ALL, 0, 0);
546
    dtlb_demap(TLB_DEMAP_ALL, 0, 0);
547
}
548
 
4055 trochtova 549
#endif
550
 
2048 jermar 551
/** Invalidate all ITLB and DTLB entries that belong to specified ASID
552
 * (Context).
617 jermar 553
 *
554
 * @param asid Address Space ID.
555
 */
556
void tlb_invalidate_asid(asid_t asid)
557
{
1865 jermar 558
    tlb_context_reg_t pc_save, ctx;
1860 jermar 559
 
1865 jermar 560
    /* switch to nucleus because we are mapped by the primary context */
561
    nucleus_enter();
562
 
563
    ctx.v = pc_save.v = mmu_primary_context_read();
1860 jermar 564
    ctx.context = asid;
1865 jermar 565
    mmu_primary_context_write(ctx.v);
1860 jermar 566
 
1865 jermar 567
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
568
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
1860 jermar 569
 
1865 jermar 570
    mmu_primary_context_write(pc_save.v);
571
 
572
    nucleus_leave();
617 jermar 573
}
574
 
2048 jermar 575
/** Invalidate all ITLB and DTLB entries for specified page range in specified
576
 * address space.
617 jermar 577
 *
4055 trochtova 578
 * @param asid      Address Space ID.
579
 * @param page      First page which to sweep out from ITLB and DTLB.
580
 * @param cnt       Number of ITLB and DTLB entries to invalidate.
617 jermar 581
 */
1780 jermar 582
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
617 jermar 583
{
2745 decky 584
    unsigned int i;
1865 jermar 585
    tlb_context_reg_t pc_save, ctx;
727 jermar 586
 
1865 jermar 587
    /* switch to nucleus because we are mapped by the primary context */
588
    nucleus_enter();
589
 
590
    ctx.v = pc_save.v = mmu_primary_context_read();
1860 jermar 591
    ctx.context = asid;
1865 jermar 592
    mmu_primary_context_write(ctx.v);
1860 jermar 593
 
2141 jermar 594
    for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) {
2134 jermar 595
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
2141 jermar 596
            page + i * MMU_PAGE_SIZE);
2134 jermar 597
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
2141 jermar 598
            page + i * MMU_PAGE_SIZE);
727 jermar 599
    }
1860 jermar 600
 
1865 jermar 601
    mmu_primary_context_write(pc_save.v);
602
 
603
    nucleus_leave();
617 jermar 604
}
1702 cejka 605
 
1792 jermar 606
/** @}
1702 cejka 607
 */