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418 jermar 1
/*
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 * Copyright (c) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup sparc64
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_sparc64_CPU_H_
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#define KERN_sparc64_CPU_H_
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#define MANUF_FUJITSU       0x04
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#define MANUF_ULTRASPARC    0x17    /**< UltraSPARC I, UltraSPARC II */
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#define MANUF_SUN       0x3e
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#define IMPL_ULTRASPARCI    0x10
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#define IMPL_ULTRASPARCII   0x11
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#define IMPL_ULTRASPARCII_I 0x12
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#define IMPL_ULTRASPARCII_E 0x13
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#define IMPL_ULTRASPARCIII  0x14
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#define IMPL_ULTRASPARCIII_PLUS 0x15
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#define IMPL_ULTRASPARCIII_I    0x16
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#define IMPL_ULTRASPARCIV   0x18
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#define IMPL_ULTRASPARCIV_PLUS  0x19
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#define IMPL_SPARC64V       0x5
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#ifndef __ASM__
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#include <arch/types.h>
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#include <typedefs.h>
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#include <arch/register.h>
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#include <arch/regdef.h>
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#include <arch/asm.h>
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#ifdef CONFIG_SMP
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#include <arch/mm/cache.h>
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#endif
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typedef struct {
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    uint32_t mid;           /**< Processor ID as read from
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                         UPA_CONFIG/FIREPLANE_CONFIG. */
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    ver_reg_t ver;
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    uint32_t clock_frequency;   /**< Processor frequency in Hz. */
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    uint64_t next_tick_cmpr;    /**< Next clock interrupt should be
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                         generated when the TICK register
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                         matches this value. */
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} cpu_arch_t;
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/**
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 * Reads the module ID (agent ID/CPUID) of the current CPU.
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 */
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static inline uint32_t read_mid(void)
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{
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    uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
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    icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
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#if defined (US)
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    return icbus_config & 0x1f;
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#elif defined (US3)
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    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I)
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        return icbus_config & 0x1f;
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    else
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        return icbus_config & 0x3ff;
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#endif
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}
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#endif  
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#endif
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/** @}
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 */