Subversion Repositories HelenOS

Rev

Rev 4055 | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
173 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
173 jermar 3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
1888 jermar 29
/** @addtogroup ia64   
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
1888 jermar 35
#ifndef KERN_ia64_ASM_H_
36
#define KERN_ia64_ASM_H_
173 jermar 37
 
747 jermar 38
#include <config.h>
4055 trochtova 39
#include <typedefs.h>
173 jermar 40
#include <arch/types.h>
432 jermar 41
#include <arch/register.h>
173 jermar 42
 
2726 vana 43
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
2515 vana 44
 
4055 trochtova 45
static inline void pio_write_8(ioport8_t *port, uint8_t v)
2515 vana 46
{
4055 trochtova 47
    uintptr_t prt = (uintptr_t) port;
2726 vana 48
 
4296 trochtova 49
    *((ioport8_t *)(IA64_IOSPACE_ADDRESS +
4055 trochtova 50
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
51
 
2515 vana 52
    asm volatile ("mf\n" ::: "memory");
53
}
54
 
4055 trochtova 55
static inline void pio_write_16(ioport16_t *port, uint16_t v)
56
{
57
    uintptr_t prt = (uintptr_t) port;
2515 vana 58
 
4296 trochtova 59
    *((ioport16_t *)(IA64_IOSPACE_ADDRESS +
4055 trochtova 60
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
61
 
62
    asm volatile ("mf\n" ::: "memory");
63
}
64
 
65
static inline void pio_write_32(ioport32_t *port, uint32_t v)
2515 vana 66
{
4055 trochtova 67
    uintptr_t prt = (uintptr_t) port;
68
 
4296 trochtova 69
    *((ioport32_t *)(IA64_IOSPACE_ADDRESS +
4055 trochtova 70
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
71
 
2515 vana 72
    asm volatile ("mf\n" ::: "memory");
4055 trochtova 73
}
2726 vana 74
 
4055 trochtova 75
static inline uint8_t pio_read_8(ioport8_t *port)
76
{
77
    uintptr_t prt = (uintptr_t) port;
78
 
79
    asm volatile ("mf\n" ::: "memory");
80
 
4296 trochtova 81
    return *((ioport8_t *)(IA64_IOSPACE_ADDRESS +
4055 trochtova 82
        ((prt & 0xfff) | ((prt >> 2) << 12))));
2515 vana 83
}
84
 
4055 trochtova 85
static inline uint16_t pio_read_16(ioport16_t *port)
86
{
87
    uintptr_t prt = (uintptr_t) port;
2515 vana 88
 
4055 trochtova 89
    asm volatile ("mf\n" ::: "memory");
2515 vana 90
 
4296 trochtova 91
    return *((ioport16_t *)(IA64_IOSPACE_ADDRESS +
4055 trochtova 92
        ((prt & 0xfff) | ((prt >> 2) << 12))));
93
}
94
 
95
static inline uint32_t pio_read_32(ioport32_t *port)
96
{
97
    uintptr_t prt = (uintptr_t) port;
98
 
99
    asm volatile ("mf\n" ::: "memory");
100
 
4296 trochtova 101
    return *((ioport32_t *)(IA64_IOSPACE_ADDRESS +
4055 trochtova 102
        ((prt & 0xfff) | ((prt >> 2) << 12))));
103
}
104
 
180 jermar 105
/** Return base address of current stack
106
 *
107
 * Return the base address of the current stack.
108
 * The stack is assumed to be STACK_SIZE long.
109
 * The stack must start on page boundary.
110
 */
1780 jermar 111
static inline uintptr_t get_stack_base(void)
173 jermar 112
{
1780 jermar 113
    uint64_t v;
180 jermar 114
 
4055 trochtova 115
    //I'm not sure why but this code bad inlines in scheduler, 
116
    //so THE shifts about 16B and causes kernel panic
117
    //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
118
    //return v;
180 jermar 119
 
4055 trochtova 120
    //this code have the same meaning but inlines well
121
    asm volatile ("mov %0 = r12" : "=r" (v)  );
122
    return v & (~(STACK_SIZE-1));
173 jermar 123
}
124
 
919 jermar 125
/** Return Processor State Register.
126
 *
127
 * @return PSR.
128
 */
1780 jermar 129
static inline uint64_t psr_read(void)
919 jermar 130
{
1780 jermar 131
    uint64_t v;
919 jermar 132
 
2082 decky 133
    asm volatile ("mov %0 = psr\n" : "=r" (v));
919 jermar 134
 
135
    return v;
136
}
137
 
470 jermar 138
/** Read IVA (Interruption Vector Address).
139
 *
140
 * @return Return location of interruption vector table.
141
 */
1780 jermar 142
static inline uint64_t iva_read(void)
470 jermar 143
{
1780 jermar 144
    uint64_t v;
470 jermar 145
 
2082 decky 146
    asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
470 jermar 147
 
148
    return v;
149
}
150
 
151
/** Write IVA (Interruption Vector Address) register.
152
 *
1708 jermar 153
 * @param v New location of interruption vector table.
470 jermar 154
 */
1780 jermar 155
static inline void iva_write(uint64_t v)
470 jermar 156
{
2082 decky 157
    asm volatile ("mov cr.iva = %0\n" : : "r" (v));
470 jermar 158
}
159
 
160
 
432 jermar 161
/** Read IVR (External Interrupt Vector Register).
431 jermar 162
 *
163
 * @return Highest priority, pending, unmasked external interrupt vector.
164
 */
1780 jermar 165
static inline uint64_t ivr_read(void)
431 jermar 166
{
1780 jermar 167
    uint64_t v;
431 jermar 168
 
2082 decky 169
    asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
431 jermar 170
 
432 jermar 171
    return v;
431 jermar 172
}
195 vana 173
 
4055 trochtova 174
static inline uint64_t cr64_read(void)
175
{
176
    uint64_t v;
177
 
178
    asm volatile ("mov %0 = cr64\n" : "=r" (v));
179
 
180
    return v;
181
}
182
 
183
 
432 jermar 184
/** Write ITC (Interval Timer Counter) register.
185
 *
1708 jermar 186
 * @param v New counter value.
432 jermar 187
 */
1780 jermar 188
static inline void itc_write(uint64_t v)
432 jermar 189
{
2082 decky 190
    asm volatile ("mov ar.itc = %0\n" : : "r" (v));
432 jermar 191
}
431 jermar 192
 
432 jermar 193
/** Read ITC (Interval Timer Counter) register.
194
 *
195
 * @return Current counter value.
196
 */
1780 jermar 197
static inline uint64_t itc_read(void)
432 jermar 198
{
1780 jermar 199
    uint64_t v;
432 jermar 200
 
2082 decky 201
    asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
432 jermar 202
 
203
    return v;
204
}
195 vana 205
 
432 jermar 206
/** Write ITM (Interval Timer Match) register.
207
 *
1708 jermar 208
 * @param v New match value.
432 jermar 209
 */
1780 jermar 210
static inline void itm_write(uint64_t v)
432 jermar 211
{
2082 decky 212
    asm volatile ("mov cr.itm = %0\n" : : "r" (v));
432 jermar 213
}
195 vana 214
 
1488 vana 215
/** Read ITM (Interval Timer Match) register.
216
 *
217
 * @return Match value.
218
 */
1780 jermar 219
static inline uint64_t itm_read(void)
1488 vana 220
{
1780 jermar 221
    uint64_t v;
1488 vana 222
 
2082 decky 223
    asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
1488 vana 224
 
225
    return v;
226
}
227
 
433 jermar 228
/** Read ITV (Interval Timer Vector) register.
229
 *
230
 * @return Current vector and mask bit.
231
 */
1780 jermar 232
static inline uint64_t itv_read(void)
433 jermar 233
{
1780 jermar 234
    uint64_t v;
433 jermar 235
 
2082 decky 236
    asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
433 jermar 237
 
238
    return v;
239
}
240
 
432 jermar 241
/** Write ITV (Interval Timer Vector) register.
242
 *
1708 jermar 243
 * @param v New vector and mask bit.
432 jermar 244
 */
1780 jermar 245
static inline void itv_write(uint64_t v)
432 jermar 246
{
2082 decky 247
    asm volatile ("mov cr.itv = %0\n" : : "r" (v));
432 jermar 248
}
238 vana 249
 
432 jermar 250
/** Write EOI (End Of Interrupt) register.
251
 *
1708 jermar 252
 * @param v This value is ignored.
432 jermar 253
 */
1780 jermar 254
static inline void eoi_write(uint64_t v)
432 jermar 255
{
2082 decky 256
    asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
432 jermar 257
}
258
 
259
/** Read TPR (Task Priority Register).
260
 *
261
 * @return Current value of TPR.
262
 */
1780 jermar 263
static inline uint64_t tpr_read(void)
432 jermar 264
{
1780 jermar 265
    uint64_t v;
432 jermar 266
 
2082 decky 267
    asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
432 jermar 268
 
269
    return v;
270
}
271
 
272
/** Write TPR (Task Priority Register).
273
 *
1708 jermar 274
 * @param v New value of TPR.
432 jermar 275
 */
1780 jermar 276
static inline void tpr_write(uint64_t v)
432 jermar 277
{
2082 decky 278
    asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
432 jermar 279
}
280
 
281
/** Disable interrupts.
282
 *
283
 * Disable interrupts and return previous
284
 * value of PSR.
285
 *
286
 * @return Old interrupt priority level.
287
 */
288
static ipl_t interrupts_disable(void)
289
{
1780 jermar 290
    uint64_t v;
432 jermar 291
 
2082 decky 292
    asm volatile (
432 jermar 293
        "mov %0 = psr\n"
294
        "rsm %1\n"
295
        : "=r" (v)
296
        : "i" (PSR_I_MASK)
297
    );
298
 
299
    return (ipl_t) v;
300
}
301
 
302
/** Enable interrupts.
303
 *
304
 * Enable interrupts and return previous
305
 * value of PSR.
306
 *
307
 * @return Old interrupt priority level.
308
 */
309
static ipl_t interrupts_enable(void)
310
{
1780 jermar 311
    uint64_t v;
432 jermar 312
 
2082 decky 313
    asm volatile (
432 jermar 314
        "mov %0 = psr\n"
315
        "ssm %1\n"
316
        ";;\n"
317
        "srlz.d\n"
318
        : "=r" (v)
319
        : "i" (PSR_I_MASK)
320
    );
321
 
322
    return (ipl_t) v;
323
}
324
 
325
/** Restore interrupt priority level.
326
 *
327
 * Restore PSR.
328
 *
329
 * @param ipl Saved interrupt priority level.
330
 */
331
static inline void interrupts_restore(ipl_t ipl)
332
{
472 jermar 333
    if (ipl & PSR_I_MASK)
334
        (void) interrupts_enable();
335
    else
336
        (void) interrupts_disable();
432 jermar 337
}
338
 
339
/** Return interrupt priority level.
340
 *
341
 * @return PSR.
342
 */
343
static inline ipl_t interrupts_read(void)
344
{
919 jermar 345
    return (ipl_t) psr_read();
432 jermar 346
}
347
 
746 jermar 348
/** Disable protection key checking. */
349
static inline void pk_disable(void)
350
{
2082 decky 351
    asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
746 jermar 352
}
353
 
432 jermar 354
extern void cpu_halt(void);
355
extern void cpu_sleep(void);
1780 jermar 356
extern void asm_delay_loop(uint32_t t);
238 vana 357
 
4055 trochtova 358
extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
359
    uint64_t, uint64_t);
919 jermar 360
 
173 jermar 361
#endif
1702 cejka 362
 
1888 jermar 363
/** @}
1702 cejka 364
 */