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1 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2001-2004 Jakub Jermar
1 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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4055 trochtova 29
/** @addtogroup ia32
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 * @{
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 */
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/** @file
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 */
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1 jermar 35
#include <arch/pm.h>
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#include <config.h>
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#include <arch/types.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <arch/context.h>
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#include <panic.h>
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#include <arch/mm/page.h>
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#include <mm/slab.h>
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#include <memstr.h>
244 decky 45
#include <arch/boot/boot.h>
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#include <interrupt.h>
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/*
11 jermar 49
 * Early ia32 configuration functions and data structures.
1 jermar 50
 */
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/*
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 * We have no use for segmentation so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 *
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 * One is for GS register which holds pointer to the TLS thread
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 * structure in it's base.
1 jermar 59
 */
1187 jermar 60
descriptor_t gdt[GDT_ITEMS] = {
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    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* KDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* UTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* UDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* TSS descriptor - set up will be completed later */
1112 palkovsky 72
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1189 jermar 73
    /* TLS descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* VESA Init descriptor */
1292 vana 76
#ifdef CONFIG_FB
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    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
1292 vana 78
#endif  
1 jermar 79
};
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1187 jermar 81
static idescriptor_t idt[IDT_ITEMS];
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1187 jermar 83
static tss_t tss;
1 jermar 84
 
1187 jermar 85
tss_t *tss_p = NULL;
1 jermar 86
 
22 jermar 87
/* gdtr is changed by kmp before next CPU is initialized */
1780 jermar 88
ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
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ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
1 jermar 90
 
1780 jermar 91
void gdt_setbase(descriptor_t *d, uintptr_t base)
1 jermar 92
{
125 jermar 93
    d->base_0_15 = base & 0xffff;
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    d->base_16_23 = ((base) >> 16) & 0xff;
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    d->base_24_31 = ((base) >> 24) & 0xff;
1 jermar 96
}
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1780 jermar 98
void gdt_setlimit(descriptor_t *d, uint32_t limit)
1 jermar 99
{
125 jermar 100
    d->limit_0_15 = limit & 0xffff;
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    d->limit_16_19 = (limit >> 16) & 0xf;
1 jermar 102
}
103
 
1780 jermar 104
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
1 jermar 105
{
112 jermar 106
    /*
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     * Offset is a linear address.
108
     */
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    d->offset_0_15 = offset & 0xffff;
110
    d->offset_16_31 = offset >> 16;
1 jermar 111
}
112
 
1187 jermar 113
void tss_initialize(tss_t *t)
1 jermar 114
{
4156 trochtova 115
    memsetb(t, sizeof(tss_t), 0);
1 jermar 116
}
117
 
118
/*
119
 * This function takes care of proper setup of IDT and IDTR.
120
 */
121
void idt_init(void)
122
{
1187 jermar 123
    idescriptor_t *d;
2227 decky 124
    unsigned int i;
125 jermar 125
 
1 jermar 126
    for (i = 0; i < IDT_ITEMS; i++) {
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        d = &idt[i];
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129
        d->unused = 0;
4156 trochtova 130
        d->selector = gdtselector(KTEXT_DES);
1 jermar 131
 
132
        d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
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        if (i == VECTOR_SYSCALL) {
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            /*
2612 jermar 136
             * The syscall interrupt gate must be calleable from
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             * userland.
1 jermar 138
             */
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            d->access |= DPL_USER;
140
        }
141
 
2612 jermar 142
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) +
143
            i * interrupt_handler_size);
1 jermar 144
    }
145
}
146
 
147
 
144 vana 148
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
141 vana 149
static void clean_IOPL_NT_flags(void)
150
{
2082 decky 151
    asm volatile (
1187 jermar 152
        "pushfl\n"
153
        "pop %%eax\n"
154
        "and $0xffff8fff, %%eax\n"
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        "push %%eax\n"
156
        "popfl\n"
4055 trochtova 157
        ::: "eax"
141 vana 158
    );
159
}
160
 
144 vana 161
/* Clean AM(18) flag in CR0 register */
143 vana 162
static void clean_AM_flag(void)
163
{
2082 decky 164
    asm volatile (
1187 jermar 165
        "mov %%cr0, %%eax\n"
166
        "and $0xfffbffff, %%eax\n"
167
        "mov %%eax, %%cr0\n"
4055 trochtova 168
        ::: "eax"
143 vana 169
    );
170
}
141 vana 171
 
1 jermar 172
void pm_init(void)
173
{
1187 jermar 174
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
175
    ptr_16_32_t idtr;
1 jermar 176
 
177
    /*
232 jermar 178
     * Update addresses in GDT and IDT to their virtual counterparts.
179
     */
271 decky 180
    idtr.limit = sizeof(idt);
1780 jermar 181
    idtr.base = (uintptr_t) idt;
1186 jermar 182
    gdtr_load(&gdtr);
183
    idtr_load(&idtr);
232 jermar 184
 
185
    /*
1 jermar 186
     * Each CPU has its private GDT and TSS.
187
     * All CPUs share one IDT.
188
     */
189
 
190
    if (config.cpu_active == 1) {
191
        idt_init();
192
        /*
193
         * NOTE: bootstrap CPU has statically allocated TSS, because
194
         * the heap hasn't been initialized so far.
195
         */
196
        tss_p = &tss;
197
    }
198
    else {
1187 jermar 199
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
1 jermar 200
        if (!tss_p)
4055 trochtova 201
            panic("Cannot allocate TSS.");
1 jermar 202
    }
203
 
204
    tss_initialize(tss_p);
205
 
206
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
207
    gdt_p[TSS_DES].special = 1;
1251 jermar 208
    gdt_p[TSS_DES].granularity = 0;
1 jermar 209
 
1780 jermar 210
    gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
1251 jermar 211
    gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
1 jermar 212
 
213
    /*
214
     * As of this moment, the current CPU has its own GDT pointing
215
     * to its own TSS. We just need to load the TR register.
216
     */
4156 trochtova 217
    tr_load(gdtselector(TSS_DES));
141 vana 218
 
1251 jermar 219
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
144 vana 220
    clean_AM_flag();          /* Disable alignment check */
1 jermar 221
}
1112 palkovsky 222
 
1780 jermar 223
void set_tls_desc(uintptr_t tls)
1112 palkovsky 224
{
1187 jermar 225
    ptr_16_32_t cpugdtr;
1188 jermar 226
    descriptor_t *gdt_p;
1112 palkovsky 227
 
1186 jermar 228
    gdtr_store(&cpugdtr);
1188 jermar 229
    gdt_p = (descriptor_t *) cpugdtr.base;
1112 palkovsky 230
    gdt_setbase(&gdt_p[TLS_DES], tls);
231
    /* Reload gdt register to update GS in CPU */
1186 jermar 232
    gdtr_load(&cpugdtr);
1112 palkovsky 233
}
1702 cejka 234
 
2227 decky 235
/* Reboot the machine by initiating
236
 * a triple fault
237
 */
238
void arch_reboot(void)
239
{
240
    preemption_disable();
241
    ipl_t ipl = interrupts_disable();
242
 
4055 trochtova 243
    memsetb(idt, sizeof(idt), 0);
2227 decky 244
 
245
    ptr_16_32_t idtr;
246
    idtr.limit = sizeof(idt);
247
    idtr.base = (uintptr_t) idt;
248
    idtr_load(&idtr);
249
 
250
    interrupts_restore(ipl);
251
    asm volatile (
252
        "int $0x03\n"
2233 decky 253
        "cli\n"
2227 decky 254
        "hlt\n"
255
    );
256
}
257
 
1888 jermar 258
/** @}
1702 cejka 259
 */