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/*
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 * Copyright (c) 2009 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup genarch
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 * @{
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 */
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/**
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 * @file
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 * @brief Headers for Zilog 8530 serial controller.
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 */
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#ifndef KERN_Z8530_H_
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#define KERN_Z8530_H_
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#include <ddi/irq.h>
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#include <arch/types.h>
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#include <console/chardev.h>
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#define WR0   0
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#define WR1   1
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#define WR2   2
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#define WR3   3
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#define WR4   4
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#define WR5   5
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#define WR6   6
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#define WR7   7
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#define WR8   8
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#define WR9   9
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#define WR10  10
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#define WR11  11
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#define WR12  12
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#define WR13  13
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#define WR14  14
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#define WR15  15
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#define RR0   0
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#define RR1   1
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#define RR2   2
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#define RR3   3
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#define RR8   8
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#define RR10  10
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#define RR12  12
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#define RR13  13
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#define RR14  14
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#define RR15  15
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/** Reset pending TX interrupt. */
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#define WR0_TX_IP_RST  (0x5 << 3)
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#define WR0_ERR_RST    (0x6 << 3)
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/** Receive Interrupts Disabled. */
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#define WR1_RID     (0x0 << 3)
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/** Receive Interrupt on First Character or Special Condition. */
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#define WR1_RIFCSC  (0x1 << 3)
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/** Interrupt on All Receive Characters or Special Conditions. */
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#define WR1_IARCSC  (0x2 << 3)
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/** Receive Interrupt on Special Condition. */
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#define WR1_RISC    (0x3 << 3)
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/** Parity Is Special Condition. */
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#define WR1_PISC    (0x1 << 2)
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/** Rx Enable. */
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#define WR3_RX_ENABLE  (0x1 << 0)
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/** 8-bits per character. */
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#define WR3_RX8BITSCH  (0x3 << 6)
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/** Master Interrupt Enable. */
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#define WR9_MIE  (0x1 << 3)
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/** Receive Character Available. */
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#define RR0_RCA  (0x1 << 0)
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/** z8530's registers. */
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typedef struct {
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    union {
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        ioport8_t ctl_b;
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        ioport8_t status_b;
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    } __attribute__ ((packed));
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    uint8_t pad1;
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    ioport8_t data_b;
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    uint8_t pad2;
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    union {
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        ioport8_t ctl_a;
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        ioport8_t status_a;
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    } __attribute__ ((packed));
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    uint8_t pad3;
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    ioport8_t data_a;
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} __attribute__ ((packed)) z8530_t;
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/** Structure representing the z8530 device. */
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typedef struct {
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    devno_t devno;
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    irq_t irq;
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    z8530_t *z8530;
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    indev_t kbrdin;
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} z8530_instance_t;
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extern devin_t *z8530_init(z8530_t *, devno_t, inr_t, cir_t, void *);
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#endif
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/** @}
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 */