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570 jermar 1
/*
2
 * Copyright (C) 2005 Jakub Jermar
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
1792 jermar 29
/** @addtogroup sparc64mm  
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
570 jermar 35
#include <arch/mm/tlb.h>
36
#include <mm/tlb.h>
1851 jermar 37
#include <mm/as.h>
38
#include <mm/asid.h>
619 jermar 39
#include <arch/mm/frame.h>
40
#include <arch/mm/page.h>
41
#include <arch/mm/mmu.h>
1851 jermar 42
#include <arch/interrupt.h>
1870 jermar 43
#include <interrupt.h>
1851 jermar 44
#include <arch.h>
570 jermar 45
#include <print.h>
617 jermar 46
#include <arch/types.h>
47
#include <typedefs.h>
619 jermar 48
#include <config.h>
630 jermar 49
#include <arch/trap/trap.h>
1880 jermar 50
#include <arch/trap/exception.h>
863 jermar 51
#include <panic.h>
873 jermar 52
#include <arch/asm.h>
894 jermar 53
 
1891 jermar 54
#ifdef CONFIG_TSB
55
#include <arch/mm/tsb.h>
56
#endif
57
 
1852 jermar 58
static void dtlb_pte_copy(pte_t *t, bool ro);
59
static void itlb_pte_copy(pte_t *t);
60
static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str);
1865 jermar 61
static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
62
static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str);
1851 jermar 63
 
873 jermar 64
char *context_encoding[] = {
65
    "Primary",
66
    "Secondary",
67
    "Nucleus",
68
    "Reserved"
69
};
70
 
570 jermar 71
void tlb_arch_init(void)
72
{
1793 jermar 73
    /*
1905 jermar 74
     * Invalidate all non-locked DTLB and ITLB entries.
1793 jermar 75
     */
1905 jermar 76
    tlb_invalidate_all();
1946 jermar 77
 
78
    /*
79
     * Clear both SFSRs.
80
     */
81
    dtlb_sfsr_write(0);
82
    itlb_sfsr_write(0);
897 jermar 83
}
873 jermar 84
 
897 jermar 85
/** Insert privileged mapping into DMMU TLB.
86
 *
87
 * @param page Virtual page address.
88
 * @param frame Physical frame address.
89
 * @param pagesize Page size.
90
 * @param locked True for permanent mappings, false otherwise.
91
 * @param cacheable True if the mapping is cacheable, false otherwise.
92
 */
1780 jermar 93
void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
897 jermar 94
{
95
    tlb_tag_access_reg_t tag;
96
    tlb_data_t data;
97
    page_address_t pg;
98
    frame_address_t fr;
873 jermar 99
 
897 jermar 100
    pg.address = page;
101
    fr.address = frame;
873 jermar 102
 
894 jermar 103
    tag.value = ASID_KERNEL;
104
    tag.vpn = pg.vpn;
105
 
106
    dtlb_tag_access_write(tag.value);
107
 
108
    data.value = 0;
109
    data.v = true;
897 jermar 110
    data.size = pagesize;
894 jermar 111
    data.pfn = fr.pfn;
897 jermar 112
    data.l = locked;
113
    data.cp = cacheable;
114
    data.cv = cacheable;
894 jermar 115
    data.p = true;
116
    data.w = true;
1868 jermar 117
    data.g = false;
894 jermar 118
 
119
    dtlb_data_in_write(data.value);
570 jermar 120
}
121
 
1852 jermar 122
/** Copy PTE to TLB.
123
 *
124
 * @param t Page Table Entry to be copied.
125
 * @param ro If true, the entry will be created read-only, regardless of its w field.
126
 */
127
void dtlb_pte_copy(pte_t *t, bool ro)
1851 jermar 128
{
1852 jermar 129
    tlb_tag_access_reg_t tag;
130
    tlb_data_t data;
131
    page_address_t pg;
132
    frame_address_t fr;
133
 
134
    pg.address = t->page;
135
    fr.address = t->frame;
136
 
137
    tag.value = 0;
138
    tag.context = t->as->asid;
139
    tag.vpn = pg.vpn;
140
 
141
    dtlb_tag_access_write(tag.value);
142
 
143
    data.value = 0;
144
    data.v = true;
145
    data.size = PAGESIZE_8K;
146
    data.pfn = fr.pfn;
147
    data.l = false;
148
    data.cp = t->c;
149
    data.cv = t->c;
1864 jermar 150
    data.p = t->k;      /* p like privileged */
1852 jermar 151
    data.w = ro ? false : t->w;
152
    data.g = t->g;
153
 
154
    dtlb_data_in_write(data.value);
1851 jermar 155
}
156
 
1891 jermar 157
/** Copy PTE to ITLB.
158
 *
159
 * @param t Page Table Entry to be copied.
160
 */
1852 jermar 161
void itlb_pte_copy(pte_t *t)
162
{
163
    tlb_tag_access_reg_t tag;
164
    tlb_data_t data;
165
    page_address_t pg;
166
    frame_address_t fr;
167
 
168
    pg.address = t->page;
169
    fr.address = t->frame;
170
 
171
    tag.value = 0;
172
    tag.context = t->as->asid;
173
    tag.vpn = pg.vpn;
174
 
175
    itlb_tag_access_write(tag.value);
176
 
177
    data.value = 0;
178
    data.v = true;
179
    data.size = PAGESIZE_8K;
180
    data.pfn = fr.pfn;
181
    data.l = false;
182
    data.cp = t->c;
183
    data.cv = t->c;
1864 jermar 184
    data.p = t->k;      /* p like privileged */
1852 jermar 185
    data.w = false;
186
    data.g = t->g;
187
 
188
    itlb_data_in_write(data.value);
189
}
190
 
863 jermar 191
/** ITLB miss handler. */
1851 jermar 192
void fast_instruction_access_mmu_miss(int n, istate_t *istate)
863 jermar 193
{
1852 jermar 194
    uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
195
    pte_t *t;
196
 
197
    page_table_lock(AS, true);
198
    t = page_mapping_find(AS, va);
199
    if (t && PTE_EXECUTABLE(t)) {
200
        /*
201
         * The mapping was found in the software page hash table.
202
         * Insert it into ITLB.
203
         */
204
        t->a = true;
205
        itlb_pte_copy(t);
1891 jermar 206
#ifdef CONFIG_TSB
207
        itsb_pte_copy(t);
208
#endif
1852 jermar 209
        page_table_unlock(AS, true);
210
    } else {
211
        /*
212
         * Forward the page fault to the address space page fault handler.
213
         */    
214
        page_table_unlock(AS, true);
215
        if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
216
            do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__);
217
        }
218
    }
863 jermar 219
}
220
 
1851 jermar 221
/** DTLB miss handler.
222
 *
223
 * Note that some faults (e.g. kernel faults) were already resolved
224
 * by the low-level, assembly language part of the fast_data_access_mmu_miss
225
 * handler.
226
 */
227
void fast_data_access_mmu_miss(int n, istate_t *istate)
863 jermar 228
{
877 jermar 229
    tlb_tag_access_reg_t tag;
1851 jermar 230
    uintptr_t va;
231
    pte_t *t;
883 jermar 232
 
877 jermar 233
    tag.value = dtlb_tag_access_read();
1865 jermar 234
    va = tag.vpn << PAGE_WIDTH;
235
 
1851 jermar 236
    if (tag.context == ASID_KERNEL) {
237
        if (!tag.vpn) {
238
            /* NULL access in kernel */
1865 jermar 239
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
1851 jermar 240
        }
1865 jermar 241
        do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault.");
1851 jermar 242
    }
873 jermar 243
 
1851 jermar 244
    page_table_lock(AS, true);
245
    t = page_mapping_find(AS, va);
246
    if (t) {
247
        /*
248
         * The mapping was found in the software page hash table.
249
         * Insert it into DTLB.
250
         */
1852 jermar 251
        t->a = true;
252
        dtlb_pte_copy(t, true);
1891 jermar 253
#ifdef CONFIG_TSB
254
        dtsb_pte_copy(t, true);
255
#endif
1851 jermar 256
        page_table_unlock(AS, true);
257
    } else {
258
        /*
259
         * Forward the page fault to the address space page fault handler.
260
         */    
261
        page_table_unlock(AS, true);
262
        if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
1865 jermar 263
            do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__);
1851 jermar 264
        }
877 jermar 265
    }
863 jermar 266
}
267
 
268
/** DTLB protection fault handler. */
1851 jermar 269
void fast_data_access_protection(int n, istate_t *istate)
863 jermar 270
{
1859 jermar 271
    tlb_tag_access_reg_t tag;
272
    uintptr_t va;
273
    pte_t *t;
274
 
275
    tag.value = dtlb_tag_access_read();
1865 jermar 276
    va = tag.vpn << PAGE_WIDTH;
1859 jermar 277
 
278
    page_table_lock(AS, true);
279
    t = page_mapping_find(AS, va);
280
    if (t && PTE_WRITABLE(t)) {
281
        /*
282
         * The mapping was found in the software page hash table and is writable.
283
         * Demap the old mapping and insert an updated mapping into DTLB.
284
         */
285
        t->a = true;
286
        t->d = true;
287
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
288
        dtlb_pte_copy(t, false);
1891 jermar 289
#ifdef CONFIG_TSB
290
        dtsb_pte_copy(t, false);
291
#endif
1859 jermar 292
        page_table_unlock(AS, true);
293
    } else {
294
        /*
295
         * Forward the page fault to the address space page fault handler.
296
         */    
297
        page_table_unlock(AS, true);
298
        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
1865 jermar 299
            do_fast_data_access_protection_fault(istate, tag, __FUNCTION__);
1859 jermar 300
        }
301
    }
863 jermar 302
}
303
 
570 jermar 304
/** Print contents of both TLBs. */
305
void tlb_print(void)
306
{
307
    int i;
308
    tlb_data_t d;
309
    tlb_tag_read_reg_t t;
310
 
311
    printf("I-TLB contents:\n");
312
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
313
        d.value = itlb_data_access_read(i);
613 jermar 314
        t.value = itlb_tag_read_read(i);
570 jermar 315
 
1735 decky 316
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
617 jermar 317
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
570 jermar 318
    }
319
 
320
    printf("D-TLB contents:\n");
321
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
322
        d.value = dtlb_data_access_read(i);
613 jermar 323
        t.value = dtlb_tag_read_read(i);
570 jermar 324
 
1735 decky 325
        printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
617 jermar 326
            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
570 jermar 327
    }
328
 
329
}
617 jermar 330
 
1852 jermar 331
void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str)
332
{
1870 jermar 333
    fault_if_from_uspace(istate, "%s\n", str);
1880 jermar 334
    dump_istate(istate);
1852 jermar 335
    panic("%s\n", str);
336
}
337
 
1865 jermar 338
void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
1851 jermar 339
{
340
    uintptr_t va;
341
 
1865 jermar 342
    va = tag.vpn << PAGE_WIDTH;
1851 jermar 343
 
1870 jermar 344
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
1880 jermar 345
    dump_istate(istate);
1851 jermar 346
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
347
    panic("%s\n", str);
348
}
349
 
1865 jermar 350
void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str)
1859 jermar 351
{
352
    uintptr_t va;
353
 
1865 jermar 354
    va = tag.vpn << PAGE_WIDTH;
1859 jermar 355
 
1870 jermar 356
    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context);
1859 jermar 357
    printf("Faulting page: %p, ASID=%d\n", va, tag.context);
1880 jermar 358
    dump_istate(istate);
1859 jermar 359
    panic("%s\n", str);
360
}
361
 
1946 jermar 362
void dump_sfsr_and_sfar(void)
363
{
364
    tlb_sfsr_reg_t sfsr;
365
    uintptr_t sfar;
366
 
367
    sfsr.value = dtlb_sfsr_read();
368
    sfar = dtlb_sfar_read();
369
 
370
    printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n",
371
        sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv);
372
    printf("DTLB SFAR: address=%p\n", sfar);
373
 
374
    dtlb_sfsr_write(0);
375
}
376
 
617 jermar 377
/** Invalidate all unlocked ITLB and DTLB entries. */
378
void tlb_invalidate_all(void)
379
{
380
    int i;
381
    tlb_data_t d;
382
    tlb_tag_read_reg_t t;
383
 
384
    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
385
        d.value = itlb_data_access_read(i);
386
        if (!d.l) {
387
            t.value = itlb_tag_read_read(i);
388
            d.v = false;
389
            itlb_tag_access_write(t.value);
390
            itlb_data_access_write(i, d.value);
391
        }
392
    }
393
 
394
    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
395
        d.value = dtlb_data_access_read(i);
396
        if (!d.l) {
397
            t.value = dtlb_tag_read_read(i);
398
            d.v = false;
399
            dtlb_tag_access_write(t.value);
400
            dtlb_data_access_write(i, d.value);
401
        }
402
    }
403
 
404
}
405
 
406
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
407
 *
408
 * @param asid Address Space ID.
409
 */
410
void tlb_invalidate_asid(asid_t asid)
411
{
1865 jermar 412
    tlb_context_reg_t pc_save, ctx;
1860 jermar 413
 
1865 jermar 414
    /* switch to nucleus because we are mapped by the primary context */
415
    nucleus_enter();
416
 
417
    ctx.v = pc_save.v = mmu_primary_context_read();
1860 jermar 418
    ctx.context = asid;
1865 jermar 419
    mmu_primary_context_write(ctx.v);
1860 jermar 420
 
1865 jermar 421
    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
422
    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0);
1860 jermar 423
 
1865 jermar 424
    mmu_primary_context_write(pc_save.v);
425
 
426
    nucleus_leave();
617 jermar 427
}
428
 
727 jermar 429
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
617 jermar 430
 *
431
 * @param asid Address Space ID.
727 jermar 432
 * @param page First page which to sweep out from ITLB and DTLB.
433
 * @param cnt Number of ITLB and DTLB entries to invalidate.
617 jermar 434
 */
1780 jermar 435
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
617 jermar 436
{
727 jermar 437
    int i;
1865 jermar 438
    tlb_context_reg_t pc_save, ctx;
727 jermar 439
 
1865 jermar 440
    /* switch to nucleus because we are mapped by the primary context */
441
    nucleus_enter();
442
 
443
    ctx.v = pc_save.v = mmu_primary_context_read();
1860 jermar 444
    ctx.context = asid;
1865 jermar 445
    mmu_primary_context_write(ctx.v);
1860 jermar 446
 
727 jermar 447
    for (i = 0; i < cnt; i++) {
1865 jermar 448
        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
449
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE);
727 jermar 450
    }
1860 jermar 451
 
1865 jermar 452
    mmu_primary_context_write(pc_save.v);
453
 
454
    nucleus_leave();
617 jermar 455
}
1702 cejka 456
 
1792 jermar 457
/** @}
1702 cejka 458
 */