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570 | jermar | 1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1792 | jermar | 29 | /** @addtogroup sparc64mm |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
570 | jermar | 35 | #include <arch/mm/tlb.h> |
36 | #include <mm/tlb.h> |
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1851 | jermar | 37 | #include <mm/as.h> |
38 | #include <mm/asid.h> |
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619 | jermar | 39 | #include <arch/mm/frame.h> |
40 | #include <arch/mm/page.h> |
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41 | #include <arch/mm/mmu.h> |
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1851 | jermar | 42 | #include <arch/interrupt.h> |
1870 | jermar | 43 | #include <interrupt.h> |
1851 | jermar | 44 | #include <arch.h> |
570 | jermar | 45 | #include <print.h> |
617 | jermar | 46 | #include <arch/types.h> |
47 | #include <typedefs.h> |
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619 | jermar | 48 | #include <config.h> |
630 | jermar | 49 | #include <arch/trap/trap.h> |
1880 | jermar | 50 | #include <arch/trap/exception.h> |
863 | jermar | 51 | #include <panic.h> |
873 | jermar | 52 | #include <arch/asm.h> |
894 | jermar | 53 | |
1891 | jermar | 54 | #ifdef CONFIG_TSB |
55 | #include <arch/mm/tsb.h> |
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56 | #endif |
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57 | |||
1852 | jermar | 58 | static void dtlb_pte_copy(pte_t *t, bool ro); |
59 | static void itlb_pte_copy(pte_t *t); |
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60 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str); |
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1865 | jermar | 61 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str); |
62 | static void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str); |
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1851 | jermar | 63 | |
873 | jermar | 64 | char *context_encoding[] = { |
65 | "Primary", |
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66 | "Secondary", |
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67 | "Nucleus", |
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68 | "Reserved" |
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69 | }; |
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70 | |||
570 | jermar | 71 | void tlb_arch_init(void) |
72 | { |
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1793 | jermar | 73 | /* |
1905 | jermar | 74 | * Invalidate all non-locked DTLB and ITLB entries. |
1793 | jermar | 75 | */ |
1905 | jermar | 76 | tlb_invalidate_all(); |
1946 | jermar | 77 | |
78 | /* |
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79 | * Clear both SFSRs. |
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80 | */ |
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81 | dtlb_sfsr_write(0); |
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82 | itlb_sfsr_write(0); |
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897 | jermar | 83 | } |
873 | jermar | 84 | |
897 | jermar | 85 | /** Insert privileged mapping into DMMU TLB. |
86 | * |
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87 | * @param page Virtual page address. |
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88 | * @param frame Physical frame address. |
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89 | * @param pagesize Page size. |
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90 | * @param locked True for permanent mappings, false otherwise. |
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91 | * @param cacheable True if the mapping is cacheable, false otherwise. |
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92 | */ |
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1780 | jermar | 93 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable) |
897 | jermar | 94 | { |
95 | tlb_tag_access_reg_t tag; |
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96 | tlb_data_t data; |
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97 | page_address_t pg; |
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98 | frame_address_t fr; |
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873 | jermar | 99 | |
897 | jermar | 100 | pg.address = page; |
101 | fr.address = frame; |
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873 | jermar | 102 | |
894 | jermar | 103 | tag.value = ASID_KERNEL; |
104 | tag.vpn = pg.vpn; |
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105 | |||
106 | dtlb_tag_access_write(tag.value); |
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107 | |||
108 | data.value = 0; |
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109 | data.v = true; |
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897 | jermar | 110 | data.size = pagesize; |
894 | jermar | 111 | data.pfn = fr.pfn; |
897 | jermar | 112 | data.l = locked; |
113 | data.cp = cacheable; |
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114 | data.cv = cacheable; |
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894 | jermar | 115 | data.p = true; |
116 | data.w = true; |
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1868 | jermar | 117 | data.g = false; |
894 | jermar | 118 | |
119 | dtlb_data_in_write(data.value); |
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570 | jermar | 120 | } |
121 | |||
1852 | jermar | 122 | /** Copy PTE to TLB. |
123 | * |
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124 | * @param t Page Table Entry to be copied. |
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125 | * @param ro If true, the entry will be created read-only, regardless of its w field. |
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126 | */ |
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127 | void dtlb_pte_copy(pte_t *t, bool ro) |
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1851 | jermar | 128 | { |
1852 | jermar | 129 | tlb_tag_access_reg_t tag; |
130 | tlb_data_t data; |
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131 | page_address_t pg; |
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132 | frame_address_t fr; |
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133 | |||
134 | pg.address = t->page; |
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135 | fr.address = t->frame; |
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136 | |||
137 | tag.value = 0; |
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138 | tag.context = t->as->asid; |
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139 | tag.vpn = pg.vpn; |
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140 | |||
141 | dtlb_tag_access_write(tag.value); |
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142 | |||
143 | data.value = 0; |
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144 | data.v = true; |
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145 | data.size = PAGESIZE_8K; |
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146 | data.pfn = fr.pfn; |
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147 | data.l = false; |
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148 | data.cp = t->c; |
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149 | data.cv = t->c; |
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1864 | jermar | 150 | data.p = t->k; /* p like privileged */ |
1852 | jermar | 151 | data.w = ro ? false : t->w; |
152 | data.g = t->g; |
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153 | |||
154 | dtlb_data_in_write(data.value); |
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1851 | jermar | 155 | } |
156 | |||
1891 | jermar | 157 | /** Copy PTE to ITLB. |
158 | * |
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159 | * @param t Page Table Entry to be copied. |
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160 | */ |
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1852 | jermar | 161 | void itlb_pte_copy(pte_t *t) |
162 | { |
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163 | tlb_tag_access_reg_t tag; |
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164 | tlb_data_t data; |
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165 | page_address_t pg; |
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166 | frame_address_t fr; |
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167 | |||
168 | pg.address = t->page; |
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169 | fr.address = t->frame; |
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170 | |||
171 | tag.value = 0; |
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172 | tag.context = t->as->asid; |
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173 | tag.vpn = pg.vpn; |
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174 | |||
175 | itlb_tag_access_write(tag.value); |
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176 | |||
177 | data.value = 0; |
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178 | data.v = true; |
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179 | data.size = PAGESIZE_8K; |
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180 | data.pfn = fr.pfn; |
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181 | data.l = false; |
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182 | data.cp = t->c; |
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183 | data.cv = t->c; |
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1864 | jermar | 184 | data.p = t->k; /* p like privileged */ |
1852 | jermar | 185 | data.w = false; |
186 | data.g = t->g; |
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187 | |||
188 | itlb_data_in_write(data.value); |
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189 | } |
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190 | |||
863 | jermar | 191 | /** ITLB miss handler. */ |
1851 | jermar | 192 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
863 | jermar | 193 | { |
1852 | jermar | 194 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
195 | pte_t *t; |
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196 | |||
197 | page_table_lock(AS, true); |
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198 | t = page_mapping_find(AS, va); |
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199 | if (t && PTE_EXECUTABLE(t)) { |
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200 | /* |
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201 | * The mapping was found in the software page hash table. |
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202 | * Insert it into ITLB. |
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203 | */ |
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204 | t->a = true; |
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205 | itlb_pte_copy(t); |
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1891 | jermar | 206 | #ifdef CONFIG_TSB |
207 | itsb_pte_copy(t); |
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208 | #endif |
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1852 | jermar | 209 | page_table_unlock(AS, true); |
210 | } else { |
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211 | /* |
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212 | * Forward the page fault to the address space page fault handler. |
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213 | */ |
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214 | page_table_unlock(AS, true); |
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215 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
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216 | do_fast_instruction_access_mmu_miss_fault(istate, __FUNCTION__); |
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217 | } |
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218 | } |
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863 | jermar | 219 | } |
220 | |||
1851 | jermar | 221 | /** DTLB miss handler. |
222 | * |
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223 | * Note that some faults (e.g. kernel faults) were already resolved |
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224 | * by the low-level, assembly language part of the fast_data_access_mmu_miss |
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225 | * handler. |
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226 | */ |
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227 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
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863 | jermar | 228 | { |
877 | jermar | 229 | tlb_tag_access_reg_t tag; |
1851 | jermar | 230 | uintptr_t va; |
231 | pte_t *t; |
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883 | jermar | 232 | |
877 | jermar | 233 | tag.value = dtlb_tag_access_read(); |
1865 | jermar | 234 | va = tag.vpn << PAGE_WIDTH; |
235 | |||
1851 | jermar | 236 | if (tag.context == ASID_KERNEL) { |
237 | if (!tag.vpn) { |
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238 | /* NULL access in kernel */ |
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1865 | jermar | 239 | do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__); |
1851 | jermar | 240 | } |
1865 | jermar | 241 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected kernel page fault."); |
1851 | jermar | 242 | } |
873 | jermar | 243 | |
1851 | jermar | 244 | page_table_lock(AS, true); |
245 | t = page_mapping_find(AS, va); |
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246 | if (t) { |
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247 | /* |
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248 | * The mapping was found in the software page hash table. |
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249 | * Insert it into DTLB. |
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250 | */ |
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1852 | jermar | 251 | t->a = true; |
252 | dtlb_pte_copy(t, true); |
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1891 | jermar | 253 | #ifdef CONFIG_TSB |
254 | dtsb_pte_copy(t, true); |
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255 | #endif |
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1851 | jermar | 256 | page_table_unlock(AS, true); |
257 | } else { |
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258 | /* |
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259 | * Forward the page fault to the address space page fault handler. |
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260 | */ |
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261 | page_table_unlock(AS, true); |
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262 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
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1865 | jermar | 263 | do_fast_data_access_mmu_miss_fault(istate, tag, __FUNCTION__); |
1851 | jermar | 264 | } |
877 | jermar | 265 | } |
863 | jermar | 266 | } |
267 | |||
268 | /** DTLB protection fault handler. */ |
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1851 | jermar | 269 | void fast_data_access_protection(int n, istate_t *istate) |
863 | jermar | 270 | { |
1859 | jermar | 271 | tlb_tag_access_reg_t tag; |
272 | uintptr_t va; |
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273 | pte_t *t; |
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274 | |||
275 | tag.value = dtlb_tag_access_read(); |
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1865 | jermar | 276 | va = tag.vpn << PAGE_WIDTH; |
1859 | jermar | 277 | |
278 | page_table_lock(AS, true); |
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279 | t = page_mapping_find(AS, va); |
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280 | if (t && PTE_WRITABLE(t)) { |
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281 | /* |
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282 | * The mapping was found in the software page hash table and is writable. |
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283 | * Demap the old mapping and insert an updated mapping into DTLB. |
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284 | */ |
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285 | t->a = true; |
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286 | t->d = true; |
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287 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va); |
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288 | dtlb_pte_copy(t, false); |
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1891 | jermar | 289 | #ifdef CONFIG_TSB |
290 | dtsb_pte_copy(t, false); |
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291 | #endif |
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1859 | jermar | 292 | page_table_unlock(AS, true); |
293 | } else { |
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294 | /* |
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295 | * Forward the page fault to the address space page fault handler. |
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296 | */ |
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297 | page_table_unlock(AS, true); |
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298 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
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1865 | jermar | 299 | do_fast_data_access_protection_fault(istate, tag, __FUNCTION__); |
1859 | jermar | 300 | } |
301 | } |
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863 | jermar | 302 | } |
303 | |||
570 | jermar | 304 | /** Print contents of both TLBs. */ |
305 | void tlb_print(void) |
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306 | { |
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307 | int i; |
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308 | tlb_data_t d; |
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309 | tlb_tag_read_reg_t t; |
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310 | |||
311 | printf("I-TLB contents:\n"); |
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312 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
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313 | d.value = itlb_data_access_read(i); |
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613 | jermar | 314 | t.value = itlb_tag_read_read(i); |
570 | jermar | 315 | |
1735 | decky | 316 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
617 | jermar | 317 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
570 | jermar | 318 | } |
319 | |||
320 | printf("D-TLB contents:\n"); |
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321 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
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322 | d.value = dtlb_data_access_read(i); |
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613 | jermar | 323 | t.value = dtlb_tag_read_read(i); |
570 | jermar | 324 | |
1735 | decky | 325 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", |
617 | jermar | 326 | i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
570 | jermar | 327 | } |
328 | |||
329 | } |
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617 | jermar | 330 | |
1852 | jermar | 331 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char *str) |
332 | { |
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1870 | jermar | 333 | fault_if_from_uspace(istate, "%s\n", str); |
1880 | jermar | 334 | dump_istate(istate); |
1852 | jermar | 335 | panic("%s\n", str); |
336 | } |
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337 | |||
1865 | jermar | 338 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str) |
1851 | jermar | 339 | { |
340 | uintptr_t va; |
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341 | |||
1865 | jermar | 342 | va = tag.vpn << PAGE_WIDTH; |
1851 | jermar | 343 | |
1870 | jermar | 344 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context); |
1880 | jermar | 345 | dump_istate(istate); |
1851 | jermar | 346 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
347 | panic("%s\n", str); |
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348 | } |
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349 | |||
1865 | jermar | 350 | void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t tag, const char *str) |
1859 | jermar | 351 | { |
352 | uintptr_t va; |
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353 | |||
1865 | jermar | 354 | va = tag.vpn << PAGE_WIDTH; |
1859 | jermar | 355 | |
1870 | jermar | 356 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, tag.context); |
1859 | jermar | 357 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
1880 | jermar | 358 | dump_istate(istate); |
1859 | jermar | 359 | panic("%s\n", str); |
360 | } |
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361 | |||
1946 | jermar | 362 | void dump_sfsr_and_sfar(void) |
363 | { |
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364 | tlb_sfsr_reg_t sfsr; |
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365 | uintptr_t sfar; |
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366 | |||
367 | sfsr.value = dtlb_sfsr_read(); |
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368 | sfar = dtlb_sfar_read(); |
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369 | |||
370 | printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, fv=%d\n", |
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371 | sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv); |
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372 | printf("DTLB SFAR: address=%p\n", sfar); |
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373 | |||
374 | dtlb_sfsr_write(0); |
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375 | } |
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376 | |||
617 | jermar | 377 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
378 | void tlb_invalidate_all(void) |
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379 | { |
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380 | int i; |
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381 | tlb_data_t d; |
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382 | tlb_tag_read_reg_t t; |
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383 | |||
384 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
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385 | d.value = itlb_data_access_read(i); |
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386 | if (!d.l) { |
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387 | t.value = itlb_tag_read_read(i); |
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388 | d.v = false; |
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389 | itlb_tag_access_write(t.value); |
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390 | itlb_data_access_write(i, d.value); |
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391 | } |
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392 | } |
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393 | |||
394 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
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395 | d.value = dtlb_data_access_read(i); |
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396 | if (!d.l) { |
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397 | t.value = dtlb_tag_read_read(i); |
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398 | d.v = false; |
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399 | dtlb_tag_access_write(t.value); |
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400 | dtlb_data_access_write(i, d.value); |
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401 | } |
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402 | } |
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403 | |||
404 | } |
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405 | |||
406 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context). |
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407 | * |
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408 | * @param asid Address Space ID. |
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409 | */ |
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410 | void tlb_invalidate_asid(asid_t asid) |
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411 | { |
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1865 | jermar | 412 | tlb_context_reg_t pc_save, ctx; |
1860 | jermar | 413 | |
1865 | jermar | 414 | /* switch to nucleus because we are mapped by the primary context */ |
415 | nucleus_enter(); |
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416 | |||
417 | ctx.v = pc_save.v = mmu_primary_context_read(); |
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1860 | jermar | 418 | ctx.context = asid; |
1865 | jermar | 419 | mmu_primary_context_write(ctx.v); |
1860 | jermar | 420 | |
1865 | jermar | 421 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
422 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
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1860 | jermar | 423 | |
1865 | jermar | 424 | mmu_primary_context_write(pc_save.v); |
425 | |||
426 | nucleus_leave(); |
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617 | jermar | 427 | } |
428 | |||
727 | jermar | 429 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
617 | jermar | 430 | * |
431 | * @param asid Address Space ID. |
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727 | jermar | 432 | * @param page First page which to sweep out from ITLB and DTLB. |
433 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
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617 | jermar | 434 | */ |
1780 | jermar | 435 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
617 | jermar | 436 | { |
727 | jermar | 437 | int i; |
1865 | jermar | 438 | tlb_context_reg_t pc_save, ctx; |
727 | jermar | 439 | |
1865 | jermar | 440 | /* switch to nucleus because we are mapped by the primary context */ |
441 | nucleus_enter(); |
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442 | |||
443 | ctx.v = pc_save.v = mmu_primary_context_read(); |
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1860 | jermar | 444 | ctx.context = asid; |
1865 | jermar | 445 | mmu_primary_context_write(ctx.v); |
1860 | jermar | 446 | |
727 | jermar | 447 | for (i = 0; i < cnt; i++) { |
1865 | jermar | 448 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE); |
449 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i * PAGE_SIZE); |
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727 | jermar | 450 | } |
1860 | jermar | 451 | |
1865 | jermar | 452 | mmu_primary_context_write(pc_save.v); |
453 | |||
454 | nucleus_leave(); |
||
617 | jermar | 455 | } |
1702 | cejka | 456 | |
1792 | jermar | 457 | /** @} |
1702 | cejka | 458 | */ |