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570 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <arch/mm/tlb.h>
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#include <mm/tlb.h>
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#include <arch/mm/frame.h>
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#include <arch/mm/page.h>
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#include <arch/mm/mmu.h>
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#include <print.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#include <config.h>
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#include <arch/trap.h>
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/** Initialize ITLB and DTLB.
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 *
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 * The goal of this function is to disable MMU
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 * so that both TLBs can be purged and new
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 * kernel 4M locked entry can be installed.
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 * After TLB is initialized, MMU is enabled
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 * again.
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 *
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 * Switching MMU off imposes the requirement for
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 * the kernel to run in identity mapped environment.
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 */
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void tlb_arch_init(void)
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{
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    tlb_tag_access_reg_t tag;
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    tlb_data_t data;
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    frame_address_t fr;
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    page_address_t pg;
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    fr.address = config.base;
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    pg.address = config.base;
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    immu_disable();
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    dmmu_disable();
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    /*
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     * For simplicity, we do identity mapping of first 4M of memory.
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     * The very next change should be leaving the first 4M unmapped.
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     */
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    tag.value = 0;
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    tag.vpn = pg.vpn;
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    itlb_tag_access_write(tag.value);
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    dtlb_tag_access_write(tag.value);
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    data.value = 0;
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    data.v = true;
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    data.size = PAGESIZE_4M;
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    data.pfn = fr.pfn;
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    data.l = true;
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    data.cp = 1;
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    data.cv = 1;
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    data.p = true;
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    data.w = true;
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    data.g = true;
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    itlb_data_in_write(data.value);
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    dtlb_data_in_write(data.value);
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    /*
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     * Register window traps can occur before MMU is enabled again.
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     * This ensures that any such traps will be handled from
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     * kernel identity mapped trap handler.
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     */
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    trap_switch_trap_table();
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    tlb_invalidate_all();
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    dmmu_enable();
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    immu_enable();
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}
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/** Print contents of both TLBs. */
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void tlb_print(void)
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{
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    int i;
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    tlb_data_t d;
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    tlb_tag_read_reg_t t;
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    printf("I-TLB contents:\n");
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    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
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        d.value = itlb_data_access_read(i);
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        t.value = itlb_tag_read_read(i);
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        printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
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            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
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    }
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    printf("D-TLB contents:\n");
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    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
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        d.value = dtlb_data_access_read(i);
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        t.value = dtlb_tag_read_read(i);
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        printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
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            i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
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    }
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}
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/** Invalidate all unlocked ITLB and DTLB entries. */
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void tlb_invalidate_all(void)
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{
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    int i;
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    tlb_data_t d;
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    tlb_tag_read_reg_t t;
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    for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
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        d.value = itlb_data_access_read(i);
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        if (!d.l) {
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            t.value = itlb_tag_read_read(i);
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            d.v = false;
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            itlb_tag_access_write(t.value);
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            itlb_data_access_write(i, d.value);
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        }
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    }
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    for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
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        d.value = dtlb_data_access_read(i);
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        if (!d.l) {
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            t.value = dtlb_tag_read_read(i);
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            d.v = false;
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            dtlb_tag_access_write(t.value);
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            dtlb_data_access_write(i, d.value);
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        }
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    }
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}
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/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
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 *
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 * @param asid Address Space ID.
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 */
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void tlb_invalidate_asid(asid_t asid)
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{
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    /* TODO: write asid to some Context register and encode the register in second parameter below. */
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    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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}
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/** Invalidate all ITLB and DLTB entries for specified page in specified address space.
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 *
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 * @param asid Address Space ID.
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 * @param page Page which to sweep out from ITLB and DTLB.
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 */
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void tlb_invalidate_page(asid_t asid, __address page)
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{
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    /* TODO: write asid to some Context register and encode the register in second parameter below. */
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    itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page);
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    dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page);
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}