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418 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __sparc64_TLB_H__
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#define __sparc64_TLB_H__
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#include <arch/mm/tte.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/page.h>
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <arch/types.h>
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#include <typedefs.h>
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569 jermar 40
#define ITLB_ENTRY_COUNT        64
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#define DTLB_ENTRY_COUNT        64
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/** Page sizes. */
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#define PAGESIZE_8K 0
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#define PAGESIZE_64K    1
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#define PAGESIZE_512K   2
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#define PAGESIZE_4M 3
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/** I-/D-TLB Data In/Access Register type. */
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typedef tte_data_t tlb_data_t;
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/** I-/D-TLB Data Access Address in Alternate Space. */
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union tlb_data_access_addr {
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    __u64 value;
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    struct {
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        __u64 : 55;
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        unsigned tlb_entry : 6;
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        unsigned : 3;
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    } __attribute__ ((packed));
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};
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typedef union tlb_data_access_addr tlb_data_access_addr_t;
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typedef union tlb_data_access_addr tlb_tag_read_addr_t;
418 jermar 63
 
569 jermar 64
/** I-/D-TLB Tag Read Register. */
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union tlb_tag_read_reg {
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    __u64 value;
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    struct {
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        __u64 vpn : 51;     /**< Virtual Address bits 63:13. */
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        unsigned context : 13;  /**< Context identifier. */
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    } __attribute__ ((packed));
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};
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typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
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typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
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/** TLB Demap Operation types. */
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#define TLB_DEMAP_PAGE      0
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#define TLB_DEMAP_CONTEXT   1
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/** TLB Demap Operation Context register encodings. */
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#define TLB_DEMAP_PRIMARY   0
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#define TLB_DEMAP_SECONDARY 1
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#define TLB_DEMAP_NUCLEUS   2
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/** TLB Demap Operation Address. */
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union tlb_demap_addr {
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    __u64 value;
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    struct {
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        __u64 vpn: 51;      /**< Virtual Address bits 63:13. */
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        unsigned : 6;       /**< Ignored. */
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        unsigned type : 1;  /**< The type of demap operation. */
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        unsigned context : 2;   /**< Context register selection. */
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        unsigned : 4;       /**< Zero. */
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    } __attribute__ ((packed));
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};
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typedef union tlb_demap_addr tlb_demap_addr_t;
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569 jermar 97
/** Read IMMU TLB Data Access Register.
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 *
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 * @param entry TLB Entry index.
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 *
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 * @return Current value of specified IMMU TLB Data Access Register.
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 */
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static inline __u64 itlb_data_access_read(index_t entry)
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{
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    tlb_data_access_addr_t reg;
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    reg.value = 0;
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    reg.tlb_entry = entry;
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    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
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}
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/** Write IMMU TLB Data Access Register.
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 *
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 * @param entry TLB Entry index.
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 * @param value Value to be written.
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 */
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static inline void itlb_data_access_write(index_t entry, __u64 value)
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{
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    tlb_data_access_addr_t reg;
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    reg.value = 0;
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    reg.tlb_entry = entry;
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    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
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    flush();
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}
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569 jermar 127
/** Read DMMU TLB Data Access Register.
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 *
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 * @param entry TLB Entry index.
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 *
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 * @return Current value of specified DMMU TLB Data Access Register.
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 */
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static inline __u64 dtlb_data_access_read(index_t entry)
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{
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    tlb_data_access_addr_t reg;
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    reg.value = 0;
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    reg.tlb_entry = entry;
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    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
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}
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617 jermar 142
/** Write DMMU TLB Data Access Register.
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 *
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 * @param entry TLB Entry index.
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 * @param value Value to be written.
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 */
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static inline void dtlb_data_access_write(index_t entry, __u64 value)
617 jermar 148
{
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    tlb_data_access_addr_t reg;
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    reg.value = 0;
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    reg.tlb_entry = entry;
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    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
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    flush();
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}
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/** Read IMMU TLB Tag Read Register.
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 *
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 * @param entry TLB Entry index.
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 *
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 * @return Current value of specified IMMU TLB Tag Read Register.
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 */
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static inline __u64 itlb_tag_read_read(index_t entry)
569 jermar 164
{
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    tlb_tag_read_addr_t tag;
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    tag.value = 0;
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    tag.tlb_entry = entry;
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    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
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}
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/** Read DMMU TLB Tag Read Register.
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 *
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 * @param entry TLB Entry index.
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 *
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 * @return Current value of specified DMMU TLB Tag Read Register.
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 */
613 jermar 178
static inline __u64 dtlb_tag_read_read(index_t entry)
569 jermar 179
{
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    tlb_tag_read_addr_t tag;
181
 
182
    tag.value = 0;
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    tag.tlb_entry = entry;
184
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
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}
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613 jermar 187
/** Write IMMU TLB Tag Access Register.
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 *
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 * @param v Value to be written.
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 */
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static inline void itlb_tag_access_write(__u64 v)
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{
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    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
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    flush();
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}
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/** Write DMMU TLB Tag Access Register.
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 *
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 * @param v Value to be written.
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 */
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static inline void dtlb_tag_access_write(__u64 v)
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{
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    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
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    flush();
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}
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/** Write IMMU TLB Data in Register.
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 *
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 * @param v Value to be written.
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 */
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static inline void itlb_data_in_write(__u64 v)
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{
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    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
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    flush();
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}
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/** Write DMMU TLB Data in Register.
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 *
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 * @param v Value to be written.
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 */
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static inline void dtlb_data_in_write(__u64 v)
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{
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    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
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    flush();
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}
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617 jermar 227
/** Perform IMMU TLB Demap Operation.
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 *
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 * @param type Selects between context and page demap.
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 * @param context_encoding Specifies which Context register has Context ID for demap.
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 * @param page Address which is on the page to be demapped.
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 */
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static inline void itlb_demap(int type, int context_encoding, __address page)
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{
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    tlb_demap_addr_t da;
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    page_address_t pg;
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    da.value = 0;
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    pg.address = page;
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    da.type = type;
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    da.context = context_encoding;
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    da.vpn = pg.vpn;
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    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
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    flush();
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}
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/** Perform DMMU TLB Demap Operation.
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 *
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 * @param type Selects between context and page demap.
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 * @param context_encoding Specifies which Context register has Context ID for demap.
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 * @param page Address which is on the page to be demapped.
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 */
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static inline void dtlb_demap(int type, int context_encoding, __address page)
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{
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    tlb_demap_addr_t da;
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    page_address_t pg;
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    da.value = 0;
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    pg.address = page;
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263
    da.type = type;
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    da.context = context_encoding;
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    da.vpn = pg.vpn;
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    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
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    flush();
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}
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418 jermar 271
#endif