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418 | jermar | 1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #ifndef __sparc64_TLB_H__ |
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30 | #define __sparc64_TLB_H__ |
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31 | |||
530 | jermar | 32 | #include <arch/mm/tte.h> |
619 | jermar | 33 | #include <arch/mm/mmu.h> |
617 | jermar | 34 | #include <arch/mm/page.h> |
569 | jermar | 35 | #include <arch/asm.h> |
613 | jermar | 36 | #include <arch/barrier.h> |
569 | jermar | 37 | #include <arch/types.h> |
38 | #include <typedefs.h> |
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530 | jermar | 39 | |
569 | jermar | 40 | #define ITLB_ENTRY_COUNT 64 |
41 | #define DTLB_ENTRY_COUNT 64 |
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42 | |||
619 | jermar | 43 | /** Page sizes. */ |
44 | #define PAGESIZE_8K 0 |
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45 | #define PAGESIZE_64K 1 |
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46 | #define PAGESIZE_512K 2 |
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47 | #define PAGESIZE_4M 3 |
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531 | jermar | 48 | |
530 | jermar | 49 | /** I-/D-TLB Data In/Access Register type. */ |
50 | typedef tte_data_t tlb_data_t; |
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51 | |||
569 | jermar | 52 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
53 | union tlb_data_access_addr { |
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54 | __u64 value; |
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55 | struct { |
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56 | __u64 : 55; |
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57 | unsigned tlb_entry : 6; |
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58 | unsigned : 3; |
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59 | } __attribute__ ((packed)); |
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60 | }; |
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61 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
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62 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
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418 | jermar | 63 | |
569 | jermar | 64 | /** I-/D-TLB Tag Read Register. */ |
65 | union tlb_tag_read_reg { |
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66 | __u64 value; |
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67 | struct { |
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617 | jermar | 68 | __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
569 | jermar | 69 | unsigned context : 13; /**< Context identifier. */ |
70 | } __attribute__ ((packed)); |
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71 | }; |
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72 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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613 | jermar | 73 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
569 | jermar | 74 | |
617 | jermar | 75 | /** TLB Demap Operation types. */ |
76 | #define TLB_DEMAP_PAGE 0 |
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77 | #define TLB_DEMAP_CONTEXT 1 |
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78 | |||
79 | /** TLB Demap Operation Context register encodings. */ |
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80 | #define TLB_DEMAP_PRIMARY 0 |
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81 | #define TLB_DEMAP_SECONDARY 1 |
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82 | #define TLB_DEMAP_NUCLEUS 2 |
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83 | |||
84 | /** TLB Demap Operation Address. */ |
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85 | union tlb_demap_addr { |
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86 | __u64 value; |
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87 | struct { |
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88 | __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
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89 | unsigned : 6; /**< Ignored. */ |
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90 | unsigned type : 1; /**< The type of demap operation. */ |
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91 | unsigned context : 2; /**< Context register selection. */ |
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92 | unsigned : 4; /**< Zero. */ |
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93 | } __attribute__ ((packed)); |
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94 | }; |
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95 | typedef union tlb_demap_addr tlb_demap_addr_t; |
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96 | |||
569 | jermar | 97 | /** Read IMMU TLB Data Access Register. |
98 | * |
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99 | * @param entry TLB Entry index. |
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100 | * |
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101 | * @return Current value of specified IMMU TLB Data Access Register. |
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102 | */ |
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103 | static inline __u64 itlb_data_access_read(index_t entry) |
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104 | { |
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105 | tlb_data_access_addr_t reg; |
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106 | |||
107 | reg.value = 0; |
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108 | reg.tlb_entry = entry; |
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109 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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110 | } |
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111 | |||
617 | jermar | 112 | /** Write IMMU TLB Data Access Register. |
113 | * |
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114 | * @param entry TLB Entry index. |
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115 | * @param value Value to be written. |
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116 | */ |
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658 | jermar | 117 | static inline void itlb_data_access_write(index_t entry, __u64 value) |
617 | jermar | 118 | { |
119 | tlb_data_access_addr_t reg; |
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120 | |||
121 | reg.value = 0; |
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122 | reg.tlb_entry = entry; |
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123 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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124 | flush(); |
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125 | } |
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126 | |||
569 | jermar | 127 | /** Read DMMU TLB Data Access Register. |
128 | * |
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129 | * @param entry TLB Entry index. |
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130 | * |
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131 | * @return Current value of specified DMMU TLB Data Access Register. |
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132 | */ |
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133 | static inline __u64 dtlb_data_access_read(index_t entry) |
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134 | { |
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135 | tlb_data_access_addr_t reg; |
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136 | |||
137 | reg.value = 0; |
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138 | reg.tlb_entry = entry; |
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139 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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140 | } |
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141 | |||
617 | jermar | 142 | /** Write DMMU TLB Data Access Register. |
143 | * |
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144 | * @param entry TLB Entry index. |
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145 | * @param value Value to be written. |
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146 | */ |
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658 | jermar | 147 | static inline void dtlb_data_access_write(index_t entry, __u64 value) |
617 | jermar | 148 | { |
149 | tlb_data_access_addr_t reg; |
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150 | |||
151 | reg.value = 0; |
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152 | reg.tlb_entry = entry; |
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153 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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154 | flush(); |
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155 | } |
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156 | |||
569 | jermar | 157 | /** Read IMMU TLB Tag Read Register. |
158 | * |
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159 | * @param entry TLB Entry index. |
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160 | * |
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161 | * @return Current value of specified IMMU TLB Tag Read Register. |
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162 | */ |
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613 | jermar | 163 | static inline __u64 itlb_tag_read_read(index_t entry) |
569 | jermar | 164 | { |
165 | tlb_tag_read_addr_t tag; |
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166 | |||
167 | tag.value = 0; |
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168 | tag.tlb_entry = entry; |
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169 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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170 | } |
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171 | |||
172 | /** Read DMMU TLB Tag Read Register. |
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173 | * |
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174 | * @param entry TLB Entry index. |
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175 | * |
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176 | * @return Current value of specified DMMU TLB Tag Read Register. |
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177 | */ |
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613 | jermar | 178 | static inline __u64 dtlb_tag_read_read(index_t entry) |
569 | jermar | 179 | { |
180 | tlb_tag_read_addr_t tag; |
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181 | |||
182 | tag.value = 0; |
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183 | tag.tlb_entry = entry; |
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184 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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185 | } |
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186 | |||
613 | jermar | 187 | /** Write IMMU TLB Tag Access Register. |
188 | * |
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189 | * @param v Value to be written. |
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190 | */ |
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191 | static inline void itlb_tag_access_write(__u64 v) |
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192 | { |
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193 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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194 | flush(); |
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195 | } |
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196 | |||
197 | /** Write DMMU TLB Tag Access Register. |
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198 | * |
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199 | * @param v Value to be written. |
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200 | */ |
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201 | static inline void dtlb_tag_access_write(__u64 v) |
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202 | { |
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203 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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204 | flush(); |
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205 | } |
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206 | |||
207 | /** Write IMMU TLB Data in Register. |
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208 | * |
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209 | * @param v Value to be written. |
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210 | */ |
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211 | static inline void itlb_data_in_write(__u64 v) |
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212 | { |
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213 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
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214 | flush(); |
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215 | } |
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216 | |||
217 | /** Write DMMU TLB Data in Register. |
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218 | * |
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219 | * @param v Value to be written. |
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220 | */ |
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221 | static inline void dtlb_data_in_write(__u64 v) |
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222 | { |
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223 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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224 | flush(); |
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225 | } |
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226 | |||
617 | jermar | 227 | /** Perform IMMU TLB Demap Operation. |
228 | * |
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229 | * @param type Selects between context and page demap. |
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230 | * @param context_encoding Specifies which Context register has Context ID for demap. |
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231 | * @param page Address which is on the page to be demapped. |
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232 | */ |
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233 | static inline void itlb_demap(int type, int context_encoding, __address page) |
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234 | { |
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235 | tlb_demap_addr_t da; |
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236 | page_address_t pg; |
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237 | |||
238 | da.value = 0; |
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239 | pg.address = page; |
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240 | |||
241 | da.type = type; |
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242 | da.context = context_encoding; |
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243 | da.vpn = pg.vpn; |
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244 | |||
245 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
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246 | flush(); |
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247 | } |
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248 | |||
249 | /** Perform DMMU TLB Demap Operation. |
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250 | * |
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251 | * @param type Selects between context and page demap. |
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252 | * @param context_encoding Specifies which Context register has Context ID for demap. |
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253 | * @param page Address which is on the page to be demapped. |
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254 | */ |
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255 | static inline void dtlb_demap(int type, int context_encoding, __address page) |
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256 | { |
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257 | tlb_demap_addr_t da; |
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258 | page_address_t pg; |
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259 | |||
260 | da.value = 0; |
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261 | pg.address = page; |
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262 | |||
263 | da.type = type; |
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264 | da.context = context_encoding; |
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265 | da.vpn = pg.vpn; |
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266 | |||
267 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
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268 | flush(); |
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269 | } |
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270 | |||
418 | jermar | 271 | #endif |