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418 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
418 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1784 | jermar | 29 | /** @addtogroup sparc64 |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
1860 | jermar | 35 | #ifndef KERN_sparc64_BARRIER_H_ |
36 | #define KERN_sparc64_BARRIER_H_ |
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418 | jermar | 37 | |
38 | /* |
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2047 | jermar | 39 | * Our critical section barriers are prepared for the weakest RMO memory model. |
418 | jermar | 40 | */ |
2047 | jermar | 41 | #define CS_ENTER_BARRIER() \ |
2272 | jermar | 42 | asm volatile ( \ |
2047 | jermar | 43 | "membar #LoadLoad | #LoadStore\n" \ |
44 | ::: "memory" \ |
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45 | ) |
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46 | #define CS_LEAVE_BARRIER() \ |
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2272 | jermar | 47 | asm volatile ( \ |
2047 | jermar | 48 | "membar #StoreStore\n" \ |
49 | "membar #LoadStore\n" \ |
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50 | ::: "memory" \ |
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51 | ) |
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418 | jermar | 52 | |
2047 | jermar | 53 | #define memory_barrier() \ |
2082 | decky | 54 | asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory") |
2047 | jermar | 55 | #define read_barrier() \ |
2082 | decky | 56 | asm volatile ("membar #LoadLoad\n" ::: "memory") |
2047 | jermar | 57 | #define write_barrier() \ |
2082 | decky | 58 | asm volatile ("membar #StoreStore\n" ::: "memory") |
418 | jermar | 59 | |
3133 | jermar | 60 | static inline void flush(uintptr_t addr) |
61 | { |
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62 | asm volatile ("flush %0\n" :: "r" (addr) : "memory"); |
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63 | } |
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64 | |||
760 | jermar | 65 | /** Flush Instruction Memory instruction. */ |
3133 | jermar | 66 | static inline void flush_blind(void) |
613 | jermar | 67 | { |
68 | /* |
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760 | jermar | 69 | * The FLUSH instruction takes address parameter. |
70 | * As such, it may trap if the address is not found in DTLB. |
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1854 | jermar | 71 | * |
72 | * The entire kernel text is mapped by a locked ITLB and |
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73 | * DTLB entries. Therefore, when this function is called, |
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74 | * the %o7 register will always be in the range mapped by |
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75 | * DTLB. |
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613 | jermar | 76 | */ |
883 | jermar | 77 | |
2082 | decky | 78 | asm volatile ("flush %o7\n"); |
613 | jermar | 79 | } |
569 | jermar | 80 | |
760 | jermar | 81 | /** Memory Barrier instruction. */ |
758 | jermar | 82 | static inline void membar(void) |
83 | { |
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2082 | decky | 84 | asm volatile ("membar #Sync\n"); |
758 | jermar | 85 | } |
86 | |||
3133 | jermar | 87 | #define smc_coherence(a) \ |
88 | { \ |
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89 | write_barrier(); \ |
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90 | flush((a)); \ |
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91 | } |
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92 | |||
418 | jermar | 93 | #endif |
1702 | cejka | 94 | |
1784 | jermar | 95 | /** @} |
1702 | cejka | 96 | */ |