Rev 2089 | Rev 3577 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
418 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
418 | jermar | 3 | * All rights reserved. |
4 | * |
||
5 | * Redistribution and use in source and binary forms, with or without |
||
6 | * modification, are permitted provided that the following conditions |
||
7 | * are met: |
||
8 | * |
||
9 | * - Redistributions of source code must retain the above copyright |
||
10 | * notice, this list of conditions and the following disclaimer. |
||
11 | * - Redistributions in binary form must reproduce the above copyright |
||
12 | * notice, this list of conditions and the following disclaimer in the |
||
13 | * documentation and/or other materials provided with the distribution. |
||
14 | * - The name of the author may not be used to endorse or promote products |
||
15 | * derived from this software without specific prior written permission. |
||
16 | * |
||
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
||
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
||
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
||
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
||
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
||
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
27 | */ |
||
28 | |||
1784 | jermar | 29 | /** @addtogroup sparc64 |
1702 | cejka | 30 | * @{ |
31 | */ |
||
32 | /** @file |
||
33 | */ |
||
34 | |||
1784 | jermar | 35 | #ifndef KERN_sparc64_ASM_H_ |
36 | #define KERN_sparc64_ASM_H_ |
||
418 | jermar | 37 | |
2089 | decky | 38 | #include <arch/arch.h> |
418 | jermar | 39 | #include <arch/types.h> |
3071 | decky | 40 | #include <typedefs.h> |
2089 | decky | 41 | #include <align.h> |
650 | jermar | 42 | #include <arch/register.h> |
418 | jermar | 43 | #include <config.h> |
1885 | jermar | 44 | #include <arch/stack.h> |
418 | jermar | 45 | |
650 | jermar | 46 | /** Read Processor State register. |
47 | * |
||
48 | * @return Value of PSTATE register. |
||
49 | */ |
||
1780 | jermar | 50 | static inline uint64_t pstate_read(void) |
650 | jermar | 51 | { |
1780 | jermar | 52 | uint64_t v; |
650 | jermar | 53 | |
2082 | decky | 54 | asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
650 | jermar | 55 | |
56 | return v; |
||
57 | } |
||
58 | |||
59 | /** Write Processor State register. |
||
60 | * |
||
1708 | jermar | 61 | * @param v New value of PSTATE register. |
650 | jermar | 62 | */ |
1780 | jermar | 63 | static inline void pstate_write(uint64_t v) |
650 | jermar | 64 | { |
2082 | decky | 65 | asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
650 | jermar | 66 | } |
67 | |||
658 | jermar | 68 | /** Read TICK_compare Register. |
69 | * |
||
70 | * @return Value of TICK_comapre register. |
||
71 | */ |
||
1780 | jermar | 72 | static inline uint64_t tick_compare_read(void) |
658 | jermar | 73 | { |
1780 | jermar | 74 | uint64_t v; |
658 | jermar | 75 | |
2082 | decky | 76 | asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
658 | jermar | 77 | |
78 | return v; |
||
79 | } |
||
650 | jermar | 80 | |
658 | jermar | 81 | /** Write TICK_compare Register. |
82 | * |
||
1708 | jermar | 83 | * @param v New value of TICK_comapre register. |
658 | jermar | 84 | */ |
1780 | jermar | 85 | static inline void tick_compare_write(uint64_t v) |
658 | jermar | 86 | { |
2082 | decky | 87 | asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
658 | jermar | 88 | } |
89 | |||
90 | /** Read TICK Register. |
||
91 | * |
||
92 | * @return Value of TICK register. |
||
93 | */ |
||
1780 | jermar | 94 | static inline uint64_t tick_read(void) |
658 | jermar | 95 | { |
1780 | jermar | 96 | uint64_t v; |
658 | jermar | 97 | |
2082 | decky | 98 | asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
658 | jermar | 99 | |
100 | return v; |
||
101 | } |
||
102 | |||
103 | /** Write TICK Register. |
||
104 | * |
||
1708 | jermar | 105 | * @param v New value of TICK register. |
658 | jermar | 106 | */ |
1780 | jermar | 107 | static inline void tick_write(uint64_t v) |
658 | jermar | 108 | { |
2082 | decky | 109 | asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
658 | jermar | 110 | } |
111 | |||
1882 | jermar | 112 | /** Read FPRS Register. |
113 | * |
||
114 | * @return Value of FPRS register. |
||
115 | */ |
||
116 | static inline uint64_t fprs_read(void) |
||
117 | { |
||
118 | uint64_t v; |
||
119 | |||
2082 | decky | 120 | asm volatile ("rd %%fprs, %0\n" : "=r" (v)); |
1882 | jermar | 121 | |
122 | return v; |
||
123 | } |
||
124 | |||
125 | /** Write FPRS Register. |
||
126 | * |
||
127 | * @param v New value of FPRS register. |
||
128 | */ |
||
129 | static inline void fprs_write(uint64_t v) |
||
130 | { |
||
2082 | decky | 131 | asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
1882 | jermar | 132 | } |
133 | |||
664 | jermar | 134 | /** Read SOFTINT Register. |
135 | * |
||
136 | * @return Value of SOFTINT register. |
||
137 | */ |
||
1780 | jermar | 138 | static inline uint64_t softint_read(void) |
664 | jermar | 139 | { |
1780 | jermar | 140 | uint64_t v; |
658 | jermar | 141 | |
2082 | decky | 142 | asm volatile ("rd %%softint, %0\n" : "=r" (v)); |
664 | jermar | 143 | |
144 | return v; |
||
145 | } |
||
146 | |||
147 | /** Write SOFTINT Register. |
||
148 | * |
||
1708 | jermar | 149 | * @param v New value of SOFTINT register. |
664 | jermar | 150 | */ |
1780 | jermar | 151 | static inline void softint_write(uint64_t v) |
664 | jermar | 152 | { |
2082 | decky | 153 | asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
664 | jermar | 154 | } |
155 | |||
665 | jermar | 156 | /** Write CLEAR_SOFTINT Register. |
157 | * |
||
158 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
||
159 | * |
||
1708 | jermar | 160 | * @param v New value of CLEAR_SOFTINT register. |
665 | jermar | 161 | */ |
1780 | jermar | 162 | static inline void clear_softint_write(uint64_t v) |
665 | jermar | 163 | { |
2082 | decky | 164 | asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
665 | jermar | 165 | } |
166 | |||
1849 | jermar | 167 | /** Write SET_SOFTINT Register. |
168 | * |
||
169 | * Bits set in SET_SOFTINT register will be set in SOFTINT register. |
||
170 | * |
||
171 | * @param v New value of SET_SOFTINT register. |
||
172 | */ |
||
173 | static inline void set_softint_write(uint64_t v) |
||
174 | { |
||
2082 | decky | 175 | asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
1849 | jermar | 176 | } |
177 | |||
418 | jermar | 178 | /** Enable interrupts. |
179 | * |
||
180 | * Enable interrupts and return previous |
||
181 | * value of IPL. |
||
182 | * |
||
183 | * @return Old interrupt priority level. |
||
184 | */ |
||
185 | static inline ipl_t interrupts_enable(void) { |
||
650 | jermar | 186 | pstate_reg_t pstate; |
1780 | jermar | 187 | uint64_t value; |
650 | jermar | 188 | |
189 | value = pstate_read(); |
||
190 | pstate.value = value; |
||
191 | pstate.ie = true; |
||
192 | pstate_write(pstate.value); |
||
193 | |||
194 | return (ipl_t) value; |
||
418 | jermar | 195 | } |
196 | |||
197 | /** Disable interrupts. |
||
198 | * |
||
199 | * Disable interrupts and return previous |
||
200 | * value of IPL. |
||
201 | * |
||
202 | * @return Old interrupt priority level. |
||
203 | */ |
||
204 | static inline ipl_t interrupts_disable(void) { |
||
650 | jermar | 205 | pstate_reg_t pstate; |
1780 | jermar | 206 | uint64_t value; |
650 | jermar | 207 | |
208 | value = pstate_read(); |
||
209 | pstate.value = value; |
||
210 | pstate.ie = false; |
||
211 | pstate_write(pstate.value); |
||
212 | |||
213 | return (ipl_t) value; |
||
418 | jermar | 214 | } |
215 | |||
216 | /** Restore interrupt priority level. |
||
217 | * |
||
218 | * Restore IPL. |
||
219 | * |
||
220 | * @param ipl Saved interrupt priority level. |
||
221 | */ |
||
222 | static inline void interrupts_restore(ipl_t ipl) { |
||
650 | jermar | 223 | pstate_reg_t pstate; |
224 | |||
225 | pstate.value = pstate_read(); |
||
226 | pstate.ie = ((pstate_reg_t) ipl).ie; |
||
227 | pstate_write(pstate.value); |
||
418 | jermar | 228 | } |
229 | |||
230 | /** Return interrupt priority level. |
||
231 | * |
||
232 | * Return IPL. |
||
233 | * |
||
234 | * @return Current interrupt priority level. |
||
235 | */ |
||
236 | static inline ipl_t interrupts_read(void) { |
||
650 | jermar | 237 | return (ipl_t) pstate_read(); |
418 | jermar | 238 | } |
239 | |||
240 | /** Return base address of current stack. |
||
241 | * |
||
242 | * Return the base address of the current stack. |
||
243 | * The stack is assumed to be STACK_SIZE bytes long. |
||
244 | * The stack must start on page boundary. |
||
245 | */ |
||
1780 | jermar | 246 | static inline uintptr_t get_stack_base(void) |
418 | jermar | 247 | { |
1885 | jermar | 248 | uintptr_t unbiased_sp; |
426 | jermar | 249 | |
2082 | decky | 250 | asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); |
426 | jermar | 251 | |
1885 | jermar | 252 | return ALIGN_DOWN(unbiased_sp, STACK_SIZE); |
418 | jermar | 253 | } |
254 | |||
640 | jermar | 255 | /** Read Version Register. |
256 | * |
||
257 | * @return Value of VER register. |
||
258 | */ |
||
1780 | jermar | 259 | static inline uint64_t ver_read(void) |
640 | jermar | 260 | { |
1780 | jermar | 261 | uint64_t v; |
640 | jermar | 262 | |
2082 | decky | 263 | asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
640 | jermar | 264 | |
265 | return v; |
||
266 | } |
||
267 | |||
2068 | jermar | 268 | /** Read Trap Program Counter register. |
529 | jermar | 269 | * |
2068 | jermar | 270 | * @return Current value in TPC. |
529 | jermar | 271 | */ |
2068 | jermar | 272 | static inline uint64_t tpc_read(void) |
529 | jermar | 273 | { |
1780 | jermar | 274 | uint64_t v; |
529 | jermar | 275 | |
2082 | decky | 276 | asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
529 | jermar | 277 | |
278 | return v; |
||
279 | } |
||
280 | |||
2068 | jermar | 281 | /** Read Trap Level register. |
873 | jermar | 282 | * |
2068 | jermar | 283 | * @return Current value in TL. |
873 | jermar | 284 | */ |
2068 | jermar | 285 | static inline uint64_t tl_read(void) |
873 | jermar | 286 | { |
1780 | jermar | 287 | uint64_t v; |
873 | jermar | 288 | |
2082 | decky | 289 | asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
873 | jermar | 290 | |
291 | return v; |
||
292 | } |
||
293 | |||
2068 | jermar | 294 | /** Read Trap Base Address register. |
883 | jermar | 295 | * |
2068 | jermar | 296 | * @return Current value in TBA. |
883 | jermar | 297 | */ |
2068 | jermar | 298 | static inline uint64_t tba_read(void) |
883 | jermar | 299 | { |
1780 | jermar | 300 | uint64_t v; |
883 | jermar | 301 | |
2082 | decky | 302 | asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
883 | jermar | 303 | |
304 | return v; |
||
305 | } |
||
873 | jermar | 306 | |
529 | jermar | 307 | /** Write Trap Base Address register. |
308 | * |
||
1708 | jermar | 309 | * @param v New value of TBA. |
529 | jermar | 310 | */ |
1780 | jermar | 311 | static inline void tba_write(uint64_t v) |
529 | jermar | 312 | { |
2082 | decky | 313 | asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
529 | jermar | 314 | } |
315 | |||
1780 | jermar | 316 | /** Load uint64_t from alternate space. |
569 | jermar | 317 | * |
318 | * @param asi ASI determining the alternate space. |
||
319 | * @param va Virtual address within the ASI. |
||
320 | * |
||
321 | * @return Value read from the virtual address in the specified address space. |
||
322 | */ |
||
1780 | jermar | 323 | static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) |
569 | jermar | 324 | { |
1780 | jermar | 325 | uint64_t v; |
569 | jermar | 326 | |
2082 | decky | 327 | asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); |
569 | jermar | 328 | |
329 | return v; |
||
330 | } |
||
529 | jermar | 331 | |
1780 | jermar | 332 | /** Store uint64_t to alternate space. |
569 | jermar | 333 | * |
334 | * @param asi ASI determining the alternate space. |
||
335 | * @param va Virtual address within the ASI. |
||
336 | * @param v Value to be written. |
||
337 | */ |
||
1780 | jermar | 338 | static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) |
569 | jermar | 339 | { |
2082 | decky | 340 | asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); |
569 | jermar | 341 | } |
342 | |||
1855 | jermar | 343 | /** Flush all valid register windows to memory. */ |
344 | static inline void flushw(void) |
||
345 | { |
||
2082 | decky | 346 | asm volatile ("flushw\n"); |
1855 | jermar | 347 | } |
348 | |||
1865 | jermar | 349 | /** Switch to nucleus by setting TL to 1. */ |
350 | static inline void nucleus_enter(void) |
||
351 | { |
||
2082 | decky | 352 | asm volatile ("wrpr %g0, 1, %tl\n"); |
1865 | jermar | 353 | } |
354 | |||
355 | /** Switch from nucleus by setting TL to 0. */ |
||
356 | static inline void nucleus_leave(void) |
||
357 | { |
||
2082 | decky | 358 | asm volatile ("wrpr %g0, %g0, %tl\n"); |
1865 | jermar | 359 | } |
360 | |||
1899 | jermar | 361 | /** Read UPA_CONFIG register. |
362 | * |
||
363 | * @return Value of the UPA_CONFIG register. |
||
364 | */ |
||
365 | static inline uint64_t upa_config_read(void) |
||
366 | { |
||
367 | return asi_u64_read(ASI_UPA_CONFIG, 0); |
||
368 | } |
||
369 | |||
1856 | jermar | 370 | extern void cpu_halt(void); |
371 | extern void cpu_sleep(void); |
||
1881 | jermar | 372 | extern void asm_delay_loop(const uint32_t usec); |
418 | jermar | 373 | |
1856 | jermar | 374 | extern uint64_t read_from_ag_g7(void); |
375 | extern void write_to_ag_g6(uint64_t val); |
||
376 | extern void write_to_ag_g7(uint64_t val); |
||
377 | extern void write_to_ig_g6(uint64_t val); |
||
378 | |||
1864 | jermar | 379 | extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); |
1860 | jermar | 380 | |
418 | jermar | 381 | #endif |
1702 | cejka | 382 | |
1784 | jermar | 383 | /** @} |
1702 | cejka | 384 | */ |