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418 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1784 jermar 29
/** @addtogroup sparc64
1702 cejka 30
 * @{
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 */
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/** @file
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 */
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1784 jermar 35
#ifndef KERN_sparc64_ASM_H_
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#define KERN_sparc64_ASM_H_
418 jermar 37
 
650 jermar 38
#include <typedefs.h>
418 jermar 39
#include <arch/types.h>
650 jermar 40
#include <arch/register.h>
418 jermar 41
#include <config.h>
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650 jermar 43
/** Read Processor State register.
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 *
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 * @return Value of PSTATE register.
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 */
1780 jermar 47
static inline uint64_t pstate_read(void)
650 jermar 48
{
1780 jermar 49
    uint64_t v;
650 jermar 50
 
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    __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
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53
    return v;
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}
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/** Write Processor State register.
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 *
1708 jermar 58
 * @param v New value of PSTATE register.
650 jermar 59
 */
1780 jermar 60
static inline void pstate_write(uint64_t v)
650 jermar 61
{
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    __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
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}
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658 jermar 65
/** Read TICK_compare Register.
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 *
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 * @return Value of TICK_comapre register.
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 */
1780 jermar 69
static inline uint64_t tick_compare_read(void)
658 jermar 70
{
1780 jermar 71
    uint64_t v;
658 jermar 72
 
73
    __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
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75
    return v;
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}
650 jermar 77
 
658 jermar 78
/** Write TICK_compare Register.
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 *
1708 jermar 80
 * @param v New value of TICK_comapre register.
658 jermar 81
 */
1780 jermar 82
static inline void tick_compare_write(uint64_t v)
658 jermar 83
{
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    __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
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}
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/** Read TICK Register.
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 *
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 * @return Value of TICK register.
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 */
1780 jermar 91
static inline uint64_t tick_read(void)
658 jermar 92
{
1780 jermar 93
    uint64_t v;
658 jermar 94
 
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    __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
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97
    return v;
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}
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/** Write TICK Register.
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 *
1708 jermar 102
 * @param v New value of TICK register.
658 jermar 103
 */
1780 jermar 104
static inline void tick_write(uint64_t v)
658 jermar 105
{
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    __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
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}
108
 
664 jermar 109
/** Read SOFTINT Register.
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 *
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 * @return Value of SOFTINT register.
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 */
1780 jermar 113
static inline uint64_t softint_read(void)
664 jermar 114
{
1780 jermar 115
    uint64_t v;
658 jermar 116
 
664 jermar 117
    __asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
118
 
119
    return v;
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}
121
 
122
/** Write SOFTINT Register.
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 *
1708 jermar 124
 * @param v New value of SOFTINT register.
664 jermar 125
 */
1780 jermar 126
static inline void softint_write(uint64_t v)
664 jermar 127
{
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    __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
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}
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665 jermar 131
/** Write CLEAR_SOFTINT Register.
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 *
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 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
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 *
1708 jermar 135
 * @param v New value of CLEAR_SOFTINT register.
665 jermar 136
 */
1780 jermar 137
static inline void clear_softint_write(uint64_t v)
665 jermar 138
{
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    __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
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}
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1849 jermar 142
/** Write SET_SOFTINT Register.
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 *
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 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
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 *
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 * @param v New value of SET_SOFTINT register.
147
 */
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static inline void set_softint_write(uint64_t v)
149
{
150
    __asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
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}
152
 
418 jermar 153
/** Enable interrupts.
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 *
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 * Enable interrupts and return previous
156
 * value of IPL.
157
 *
158
 * @return Old interrupt priority level.
159
 */
160
static inline ipl_t interrupts_enable(void) {
650 jermar 161
    pstate_reg_t pstate;
1780 jermar 162
    uint64_t value;
650 jermar 163
 
164
    value = pstate_read();
165
    pstate.value = value;
166
    pstate.ie = true;
167
    pstate_write(pstate.value);
168
 
169
    return (ipl_t) value;
418 jermar 170
}
171
 
172
/** Disable interrupts.
173
 *
174
 * Disable interrupts and return previous
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 * value of IPL.
176
 *
177
 * @return Old interrupt priority level.
178
 */
179
static inline ipl_t interrupts_disable(void) {
650 jermar 180
    pstate_reg_t pstate;
1780 jermar 181
    uint64_t value;
650 jermar 182
 
183
    value = pstate_read();
184
    pstate.value = value;
185
    pstate.ie = false;
186
    pstate_write(pstate.value);
187
 
188
    return (ipl_t) value;
418 jermar 189
}
190
 
191
/** Restore interrupt priority level.
192
 *
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 * Restore IPL.
194
 *
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 * @param ipl Saved interrupt priority level.
196
 */
197
static inline void interrupts_restore(ipl_t ipl) {
650 jermar 198
    pstate_reg_t pstate;
199
 
200
    pstate.value = pstate_read();
201
    pstate.ie = ((pstate_reg_t) ipl).ie;
202
    pstate_write(pstate.value);
418 jermar 203
}
204
 
205
/** Return interrupt priority level.
206
 *
207
 * Return IPL.
208
 *
209
 * @return Current interrupt priority level.
210
 */
211
static inline ipl_t interrupts_read(void) {
650 jermar 212
    return (ipl_t) pstate_read();
418 jermar 213
}
214
 
215
/** Return base address of current stack.
216
 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE bytes long.
219
 * The stack must start on page boundary.
220
 */
1780 jermar 221
static inline uintptr_t get_stack_base(void)
418 jermar 222
{
1780 jermar 223
    uintptr_t v;
426 jermar 224
 
650 jermar 225
    __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
426 jermar 226
 
227
    return v;
418 jermar 228
}
229
 
640 jermar 230
/** Read Version Register.
231
 *
232
 * @return Value of VER register.
233
 */
1780 jermar 234
static inline uint64_t ver_read(void)
640 jermar 235
{
1780 jermar 236
    uint64_t v;
640 jermar 237
 
238
    __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
239
 
240
    return v;
241
}
242
 
529 jermar 243
/** Read Trap Base Address register.
244
 *
245
 * @return Current value in TBA.
246
 */
1780 jermar 247
static inline uint64_t tba_read(void)
529 jermar 248
{
1780 jermar 249
    uint64_t v;
529 jermar 250
 
251
    __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
252
 
253
    return v;
254
}
255
 
873 jermar 256
/** Read Trap Program Counter register.
257
 *
258
 * @return Current value in TPC.
259
 */
1780 jermar 260
static inline uint64_t tpc_read(void)
873 jermar 261
{
1780 jermar 262
    uint64_t v;
873 jermar 263
 
264
    __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
265
 
266
    return v;
267
}
268
 
883 jermar 269
/** Read Trap Level register.
270
 *
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 * @return Current value in TL.
272
 */
1780 jermar 273
static inline uint64_t tl_read(void)
883 jermar 274
{
1780 jermar 275
    uint64_t v;
883 jermar 276
 
277
    __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
278
 
279
    return v;
280
}
873 jermar 281
 
529 jermar 282
/** Write Trap Base Address register.
283
 *
1708 jermar 284
 * @param v New value of TBA.
529 jermar 285
 */
1780 jermar 286
static inline void tba_write(uint64_t v)
529 jermar 287
{
288
    __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
289
}
290
 
1780 jermar 291
/** Load uint64_t from alternate space.
569 jermar 292
 *
293
 * @param asi ASI determining the alternate space.
294
 * @param va Virtual address within the ASI.
295
 *
296
 * @return Value read from the virtual address in the specified address space.
297
 */
1780 jermar 298
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
569 jermar 299
{
1780 jermar 300
    uint64_t v;
569 jermar 301
 
302
    __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
303
 
304
    return v;
305
}
529 jermar 306
 
1780 jermar 307
/** Store uint64_t to alternate space.
569 jermar 308
 *
309
 * @param asi ASI determining the alternate space.
310
 * @param va Virtual address within the ASI.
311
 * @param v Value to be written.
312
 */
1780 jermar 313
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
569 jermar 314
{
613 jermar 315
    __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
569 jermar 316
}
317
 
1855 jermar 318
/** Flush all valid register windows to memory. */
319
static inline void flushw(void)
320
{
321
    __asm__ volatile ("flushw\n");
322
}
323
 
1856 jermar 324
extern void cpu_halt(void);
325
extern void cpu_sleep(void);
326
extern void asm_delay_loop(uint32_t t);
418 jermar 327
 
1856 jermar 328
extern uint64_t read_from_ag_g7(void);
329
extern void write_to_ag_g6(uint64_t val);
330
extern void write_to_ag_g7(uint64_t val);
331
extern void write_to_ig_g6(uint64_t val);
332
 
418 jermar 333
#endif
1702 cejka 334
 
1784 jermar 335
/** @}
1702 cejka 336
 */