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1 | jermar | 1 | /* |
319 | jermar | 2 | * Copyright (C) 2003-2004 Jakub Jermar |
1 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #include <arch/mm/tlb.h> |
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727 | jermar | 30 | #include <mm/asid.h> |
1 | jermar | 31 | #include <mm/tlb.h> |
391 | jermar | 32 | #include <mm/page.h> |
703 | jermar | 33 | #include <mm/as.h> |
1 | jermar | 34 | #include <arch/cp0.h> |
35 | #include <panic.h> |
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36 | #include <arch.h> |
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268 | palkovsky | 37 | #include <symtab.h> |
391 | jermar | 38 | #include <synch/spinlock.h> |
39 | #include <print.h> |
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396 | jermar | 40 | #include <debug.h> |
983 | palkovsky | 41 | #include <align.h> |
268 | palkovsky | 42 | |
958 | jermar | 43 | static void tlb_refill_fail(istate_t *istate); |
44 | static void tlb_invalid_fail(istate_t *istate); |
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45 | static void tlb_modified_fail(istate_t *istate); |
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391 | jermar | 46 | |
1411 | jermar | 47 | static pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc); |
399 | jermar | 48 | |
831 | jermar | 49 | static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn); |
399 | jermar | 50 | static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr); |
394 | jermar | 51 | |
391 | jermar | 52 | /** Initialize TLB |
53 | * |
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54 | * Initialize TLB. |
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55 | * Invalidate all entries and mark wired entries. |
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56 | */ |
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569 | jermar | 57 | void tlb_arch_init(void) |
389 | jermar | 58 | { |
599 | jermar | 59 | int i; |
60 | |||
389 | jermar | 61 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
599 | jermar | 62 | cp0_entry_hi_write(0); |
63 | cp0_entry_lo0_write(0); |
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64 | cp0_entry_lo1_write(0); |
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389 | jermar | 65 | |
599 | jermar | 66 | /* Clear and initialize TLB. */ |
67 | |||
68 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
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69 | cp0_index_write(i); |
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70 | tlbwi(); |
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71 | } |
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612 | jermar | 72 | |
598 | jermar | 73 | |
389 | jermar | 74 | /* |
75 | * The kernel is going to make use of some wired |
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391 | jermar | 76 | * entries (e.g. mapping kernel stacks in kseg3). |
389 | jermar | 77 | */ |
78 | cp0_wired_write(TLB_WIRED); |
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79 | } |
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80 | |||
391 | jermar | 81 | /** Process TLB Refill Exception |
82 | * |
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83 | * Process TLB Refill Exception. |
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84 | * |
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958 | jermar | 85 | * @param istate Interrupted register context. |
391 | jermar | 86 | */ |
958 | jermar | 87 | void tlb_refill(istate_t *istate) |
1 | jermar | 88 | { |
396 | jermar | 89 | entry_lo_t lo; |
1044 | jermar | 90 | entry_hi_t hi; |
91 | asid_t asid; |
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391 | jermar | 92 | __address badvaddr; |
93 | pte_t *pte; |
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1288 | jermar | 94 | int pfrc; |
397 | jermar | 95 | |
391 | jermar | 96 | badvaddr = cp0_badvaddr_read(); |
397 | jermar | 97 | |
1044 | jermar | 98 | spinlock_lock(&AS->lock); |
99 | asid = AS->asid; |
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100 | spinlock_unlock(&AS->lock); |
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399 | jermar | 101 | |
1044 | jermar | 102 | page_table_lock(AS, true); |
103 | |||
1411 | jermar | 104 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
1288 | jermar | 105 | if (!pte) { |
106 | switch (pfrc) { |
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107 | case AS_PF_FAULT: |
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108 | goto fail; |
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109 | break; |
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110 | case AS_PF_DEFER: |
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111 | /* |
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112 | * The page fault came during copy_from_uspace() |
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113 | * or copy_to_uspace(). |
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114 | */ |
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115 | page_table_unlock(AS, true); |
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116 | return; |
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117 | default: |
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118 | panic("unexpected pfrc (%d)\n", pfrc); |
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119 | } |
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120 | } |
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391 | jermar | 121 | |
122 | /* |
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394 | jermar | 123 | * Record access to PTE. |
391 | jermar | 124 | */ |
394 | jermar | 125 | pte->a = 1; |
391 | jermar | 126 | |
1044 | jermar | 127 | prepare_entry_hi(&hi, asid, badvaddr); |
831 | jermar | 128 | prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
394 | jermar | 129 | |
391 | jermar | 130 | /* |
131 | * New entry is to be inserted into TLB |
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132 | */ |
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399 | jermar | 133 | cp0_entry_hi_write(hi.value); |
391 | jermar | 134 | if ((badvaddr/PAGE_SIZE) % 2 == 0) { |
396 | jermar | 135 | cp0_entry_lo0_write(lo.value); |
391 | jermar | 136 | cp0_entry_lo1_write(0); |
137 | } |
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138 | else { |
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139 | cp0_entry_lo0_write(0); |
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396 | jermar | 140 | cp0_entry_lo1_write(lo.value); |
391 | jermar | 141 | } |
612 | jermar | 142 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
391 | jermar | 143 | tlbwr(); |
144 | |||
1044 | jermar | 145 | page_table_unlock(AS, true); |
391 | jermar | 146 | return; |
147 | |||
148 | fail: |
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1044 | jermar | 149 | page_table_unlock(AS, true); |
958 | jermar | 150 | tlb_refill_fail(istate); |
391 | jermar | 151 | } |
152 | |||
394 | jermar | 153 | /** Process TLB Invalid Exception |
154 | * |
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155 | * Process TLB Invalid Exception. |
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156 | * |
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958 | jermar | 157 | * @param istate Interrupted register context. |
394 | jermar | 158 | */ |
958 | jermar | 159 | void tlb_invalid(istate_t *istate) |
391 | jermar | 160 | { |
396 | jermar | 161 | tlb_index_t index; |
394 | jermar | 162 | __address badvaddr; |
396 | jermar | 163 | entry_lo_t lo; |
399 | jermar | 164 | entry_hi_t hi; |
394 | jermar | 165 | pte_t *pte; |
1288 | jermar | 166 | int pfrc; |
394 | jermar | 167 | |
168 | badvaddr = cp0_badvaddr_read(); |
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169 | |||
170 | /* |
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171 | * Locate the faulting entry in TLB. |
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172 | */ |
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399 | jermar | 173 | hi.value = cp0_entry_hi_read(); |
174 | prepare_entry_hi(&hi, hi.asid, badvaddr); |
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175 | cp0_entry_hi_write(hi.value); |
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394 | jermar | 176 | tlbp(); |
396 | jermar | 177 | index.value = cp0_index_read(); |
1044 | jermar | 178 | |
179 | page_table_lock(AS, true); |
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394 | jermar | 180 | |
181 | /* |
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182 | * Fail if the entry is not in TLB. |
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183 | */ |
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396 | jermar | 184 | if (index.p) { |
185 | printf("TLB entry not found.\n"); |
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394 | jermar | 186 | goto fail; |
396 | jermar | 187 | } |
394 | jermar | 188 | |
1411 | jermar | 189 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc); |
1288 | jermar | 190 | if (!pte) { |
191 | switch (pfrc) { |
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192 | case AS_PF_FAULT: |
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193 | goto fail; |
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194 | break; |
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195 | case AS_PF_DEFER: |
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196 | /* |
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197 | * The page fault came during copy_from_uspace() |
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198 | * or copy_to_uspace(). |
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199 | */ |
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200 | page_table_unlock(AS, true); |
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201 | return; |
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202 | default: |
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203 | panic("unexpected pfrc (%d)\n", pfrc); |
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204 | } |
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205 | } |
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394 | jermar | 206 | |
207 | /* |
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208 | * Read the faulting TLB entry. |
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209 | */ |
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210 | tlbr(); |
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211 | |||
212 | /* |
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213 | * Record access to PTE. |
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214 | */ |
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215 | pte->a = 1; |
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216 | |||
831 | jermar | 217 | prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); |
394 | jermar | 218 | |
219 | /* |
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220 | * The entry is to be updated in TLB. |
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221 | */ |
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222 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
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396 | jermar | 223 | cp0_entry_lo0_write(lo.value); |
394 | jermar | 224 | else |
396 | jermar | 225 | cp0_entry_lo1_write(lo.value); |
612 | jermar | 226 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
394 | jermar | 227 | tlbwi(); |
228 | |||
1044 | jermar | 229 | page_table_unlock(AS, true); |
394 | jermar | 230 | return; |
231 | |||
232 | fail: |
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1044 | jermar | 233 | page_table_unlock(AS, true); |
958 | jermar | 234 | tlb_invalid_fail(istate); |
391 | jermar | 235 | } |
236 | |||
394 | jermar | 237 | /** Process TLB Modified Exception |
238 | * |
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239 | * Process TLB Modified Exception. |
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240 | * |
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958 | jermar | 241 | * @param istate Interrupted register context. |
394 | jermar | 242 | */ |
958 | jermar | 243 | void tlb_modified(istate_t *istate) |
391 | jermar | 244 | { |
396 | jermar | 245 | tlb_index_t index; |
394 | jermar | 246 | __address badvaddr; |
396 | jermar | 247 | entry_lo_t lo; |
399 | jermar | 248 | entry_hi_t hi; |
394 | jermar | 249 | pte_t *pte; |
1288 | jermar | 250 | int pfrc; |
394 | jermar | 251 | |
252 | badvaddr = cp0_badvaddr_read(); |
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253 | |||
254 | /* |
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255 | * Locate the faulting entry in TLB. |
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256 | */ |
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399 | jermar | 257 | hi.value = cp0_entry_hi_read(); |
258 | prepare_entry_hi(&hi, hi.asid, badvaddr); |
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259 | cp0_entry_hi_write(hi.value); |
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394 | jermar | 260 | tlbp(); |
396 | jermar | 261 | index.value = cp0_index_read(); |
1044 | jermar | 262 | |
263 | page_table_lock(AS, true); |
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394 | jermar | 264 | |
265 | /* |
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266 | * Fail if the entry is not in TLB. |
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267 | */ |
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396 | jermar | 268 | if (index.p) { |
269 | printf("TLB entry not found.\n"); |
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394 | jermar | 270 | goto fail; |
396 | jermar | 271 | } |
394 | jermar | 272 | |
1411 | jermar | 273 | pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc); |
1288 | jermar | 274 | if (!pte) { |
275 | switch (pfrc) { |
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276 | case AS_PF_FAULT: |
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277 | goto fail; |
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278 | break; |
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279 | case AS_PF_DEFER: |
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280 | /* |
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281 | * The page fault came during copy_from_uspace() |
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282 | * or copy_to_uspace(). |
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283 | */ |
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284 | page_table_unlock(AS, true); |
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285 | return; |
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286 | default: |
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287 | panic("unexpected pfrc (%d)\n", pfrc); |
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288 | } |
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289 | } |
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394 | jermar | 290 | |
291 | /* |
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292 | * Fail if the page is not writable. |
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293 | */ |
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294 | if (!pte->w) |
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295 | goto fail; |
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296 | |||
297 | /* |
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298 | * Read the faulting TLB entry. |
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299 | */ |
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300 | tlbr(); |
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301 | |||
302 | /* |
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303 | * Record access and write to PTE. |
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304 | */ |
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305 | pte->a = 1; |
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831 | jermar | 306 | pte->d = 1; |
394 | jermar | 307 | |
831 | jermar | 308 | prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn); |
394 | jermar | 309 | |
310 | /* |
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311 | * The entry is to be updated in TLB. |
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312 | */ |
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313 | if ((badvaddr/PAGE_SIZE) % 2 == 0) |
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396 | jermar | 314 | cp0_entry_lo0_write(lo.value); |
394 | jermar | 315 | else |
396 | jermar | 316 | cp0_entry_lo1_write(lo.value); |
612 | jermar | 317 | cp0_pagemask_write(TLB_PAGE_MASK_16K); |
394 | jermar | 318 | tlbwi(); |
319 | |||
1044 | jermar | 320 | page_table_unlock(AS, true); |
394 | jermar | 321 | return; |
322 | |||
323 | fail: |
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1044 | jermar | 324 | page_table_unlock(AS, true); |
958 | jermar | 325 | tlb_modified_fail(istate); |
391 | jermar | 326 | } |
327 | |||
958 | jermar | 328 | void tlb_refill_fail(istate_t *istate) |
391 | jermar | 329 | { |
324 | palkovsky | 330 | char *symbol = ""; |
331 | char *sym2 = ""; |
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332 | |||
958 | jermar | 333 | char *s = get_symtab_entry(istate->epc); |
332 | palkovsky | 334 | if (s) |
335 | symbol = s; |
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958 | jermar | 336 | s = get_symtab_entry(istate->ra); |
332 | palkovsky | 337 | if (s) |
338 | sym2 = s; |
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958 | jermar | 339 | panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2); |
1 | jermar | 340 | } |
341 | |||
391 | jermar | 342 | |
958 | jermar | 343 | void tlb_invalid_fail(istate_t *istate) |
1 | jermar | 344 | { |
268 | palkovsky | 345 | char *symbol = ""; |
346 | |||
958 | jermar | 347 | char *s = get_symtab_entry(istate->epc); |
332 | palkovsky | 348 | if (s) |
349 | symbol = s; |
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958 | jermar | 350 | panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol); |
1 | jermar | 351 | } |
352 | |||
958 | jermar | 353 | void tlb_modified_fail(istate_t *istate) |
389 | jermar | 354 | { |
355 | char *symbol = ""; |
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356 | |||
958 | jermar | 357 | char *s = get_symtab_entry(istate->epc); |
389 | jermar | 358 | if (s) |
359 | symbol = s; |
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958 | jermar | 360 | panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol); |
389 | jermar | 361 | } |
362 | |||
394 | jermar | 363 | /** Try to find PTE for faulting address |
364 | * |
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365 | * Try to find PTE for faulting address. |
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703 | jermar | 366 | * The AS->lock must be held on entry to this function. |
394 | jermar | 367 | * |
368 | * @param badvaddr Faulting virtual address. |
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1411 | jermar | 369 | * @param access Access mode that caused the fault. |
1288 | jermar | 370 | * @param istate Pointer to interrupted state. |
371 | * @param pfrc Pointer to variable where as_page_fault() return code will be stored. |
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394 | jermar | 372 | * |
373 | * @return PTE on success, NULL otherwise. |
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374 | */ |
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1411 | jermar | 375 | pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc) |
394 | jermar | 376 | { |
396 | jermar | 377 | entry_hi_t hi; |
394 | jermar | 378 | pte_t *pte; |
379 | |||
396 | jermar | 380 | hi.value = cp0_entry_hi_read(); |
394 | jermar | 381 | |
382 | /* |
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383 | * Handler cannot succeed if the ASIDs don't match. |
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384 | */ |
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703 | jermar | 385 | if (hi.asid != AS->asid) { |
386 | printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid); |
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394 | jermar | 387 | return NULL; |
396 | jermar | 388 | } |
703 | jermar | 389 | |
394 | jermar | 390 | /* |
703 | jermar | 391 | * Check if the mapping exists in page tables. |
392 | */ |
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756 | jermar | 393 | pte = page_mapping_find(AS, badvaddr); |
831 | jermar | 394 | if (pte && pte->p) { |
703 | jermar | 395 | /* |
396 | * Mapping found in page tables. |
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397 | * Immediately succeed. |
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398 | */ |
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399 | return pte; |
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400 | } else { |
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1288 | jermar | 401 | int rc; |
402 | |||
703 | jermar | 403 | /* |
404 | * Mapping not found in page tables. |
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405 | * Resort to higher-level page fault handler. |
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406 | */ |
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1044 | jermar | 407 | page_table_unlock(AS, true); |
1411 | jermar | 408 | switch (rc = as_page_fault(badvaddr, access, istate)) { |
1288 | jermar | 409 | case AS_PF_OK: |
703 | jermar | 410 | /* |
411 | * The higher-level page fault handler succeeded, |
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412 | * The mapping ought to be in place. |
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413 | */ |
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1044 | jermar | 414 | page_table_lock(AS, true); |
756 | jermar | 415 | pte = page_mapping_find(AS, badvaddr); |
831 | jermar | 416 | ASSERT(pte && pte->p); |
703 | jermar | 417 | return pte; |
1288 | jermar | 418 | break; |
419 | case AS_PF_DEFER: |
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1044 | jermar | 420 | page_table_lock(AS, true); |
1288 | jermar | 421 | *pfrc = AS_PF_DEFER; |
422 | return NULL; |
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423 | break; |
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424 | case AS_PF_FAULT: |
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425 | page_table_lock(AS, true); |
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1044 | jermar | 426 | printf("Page fault.\n"); |
1288 | jermar | 427 | *pfrc = AS_PF_FAULT; |
1044 | jermar | 428 | return NULL; |
1288 | jermar | 429 | break; |
430 | default: |
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431 | panic("unexpected rc (%d)\n", rc); |
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703 | jermar | 432 | } |
1044 | jermar | 433 | |
703 | jermar | 434 | } |
394 | jermar | 435 | } |
436 | |||
831 | jermar | 437 | void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn) |
394 | jermar | 438 | { |
399 | jermar | 439 | lo->value = 0; |
394 | jermar | 440 | lo->g = g; |
441 | lo->v = v; |
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442 | lo->d = d; |
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831 | jermar | 443 | lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; |
394 | jermar | 444 | lo->pfn = pfn; |
445 | } |
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399 | jermar | 446 | |
447 | void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr) |
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448 | { |
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983 | palkovsky | 449 | hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); |
399 | jermar | 450 | hi->asid = asid; |
451 | } |
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569 | jermar | 452 | |
594 | jermar | 453 | /** Print contents of TLB. */ |
569 | jermar | 454 | void tlb_print(void) |
455 | { |
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612 | jermar | 456 | page_mask_t mask; |
594 | jermar | 457 | entry_lo_t lo0, lo1; |
704 | jermar | 458 | entry_hi_t hi, hi_save; |
594 | jermar | 459 | int i; |
460 | |||
704 | jermar | 461 | hi_save.value = cp0_entry_hi_read(); |
462 | |||
594 | jermar | 463 | printf("TLB:\n"); |
464 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
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465 | cp0_index_write(i); |
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466 | tlbr(); |
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467 | |||
612 | jermar | 468 | mask.value = cp0_pagemask_read(); |
594 | jermar | 469 | hi.value = cp0_entry_hi_read(); |
470 | lo0.value = cp0_entry_lo0_read(); |
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471 | lo1.value = cp0_entry_lo1_read(); |
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472 | |||
1196 | cejka | 473 | printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n" |
474 | "\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n", |
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612 | jermar | 475 | i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn, |
594 | jermar | 476 | lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn); |
477 | } |
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704 | jermar | 478 | |
479 | cp0_entry_hi_write(hi_save.value); |
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569 | jermar | 480 | } |
598 | jermar | 481 | |
618 | jermar | 482 | /** Invalidate all not wired TLB entries. */ |
598 | jermar | 483 | void tlb_invalidate_all(void) |
484 | { |
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599 | jermar | 485 | ipl_t ipl; |
486 | entry_lo_t lo0, lo1; |
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704 | jermar | 487 | entry_hi_t hi_save; |
598 | jermar | 488 | int i; |
489 | |||
704 | jermar | 490 | hi_save.value = cp0_entry_hi_read(); |
599 | jermar | 491 | ipl = interrupts_disable(); |
598 | jermar | 492 | |
618 | jermar | 493 | for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { |
598 | jermar | 494 | cp0_index_write(i); |
599 | jermar | 495 | tlbr(); |
496 | |||
497 | lo0.value = cp0_entry_lo0_read(); |
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498 | lo1.value = cp0_entry_lo1_read(); |
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499 | |||
500 | lo0.v = 0; |
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501 | lo1.v = 0; |
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502 | |||
503 | cp0_entry_lo0_write(lo0.value); |
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504 | cp0_entry_lo1_write(lo1.value); |
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505 | |||
598 | jermar | 506 | tlbwi(); |
507 | } |
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599 | jermar | 508 | |
509 | interrupts_restore(ipl); |
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704 | jermar | 510 | cp0_entry_hi_write(hi_save.value); |
598 | jermar | 511 | } |
512 | |||
513 | /** Invalidate all TLB entries belonging to specified address space. |
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514 | * |
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515 | * @param asid Address space identifier. |
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516 | */ |
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517 | void tlb_invalidate_asid(asid_t asid) |
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518 | { |
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599 | jermar | 519 | ipl_t ipl; |
520 | entry_lo_t lo0, lo1; |
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704 | jermar | 521 | entry_hi_t hi, hi_save; |
598 | jermar | 522 | int i; |
523 | |||
599 | jermar | 524 | ASSERT(asid != ASID_INVALID); |
525 | |||
704 | jermar | 526 | hi_save.value = cp0_entry_hi_read(); |
599 | jermar | 527 | ipl = interrupts_disable(); |
528 | |||
598 | jermar | 529 | for (i = 0; i < TLB_ENTRY_COUNT; i++) { |
530 | cp0_index_write(i); |
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531 | tlbr(); |
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532 | |||
599 | jermar | 533 | hi.value = cp0_entry_hi_read(); |
534 | |||
598 | jermar | 535 | if (hi.asid == asid) { |
599 | jermar | 536 | lo0.value = cp0_entry_lo0_read(); |
537 | lo1.value = cp0_entry_lo1_read(); |
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538 | |||
539 | lo0.v = 0; |
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540 | lo1.v = 0; |
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541 | |||
542 | cp0_entry_lo0_write(lo0.value); |
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543 | cp0_entry_lo1_write(lo1.value); |
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544 | |||
598 | jermar | 545 | tlbwi(); |
546 | } |
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547 | } |
||
599 | jermar | 548 | |
549 | interrupts_restore(ipl); |
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704 | jermar | 550 | cp0_entry_hi_write(hi_save.value); |
598 | jermar | 551 | } |
552 | |||
727 | jermar | 553 | /** Invalidate TLB entries for specified page range belonging to specified address space. |
598 | jermar | 554 | * |
555 | * @param asid Address space identifier. |
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727 | jermar | 556 | * @param page First page whose TLB entry is to be invalidated. |
557 | * @param cnt Number of entries to invalidate. |
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598 | jermar | 558 | */ |
727 | jermar | 559 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
598 | jermar | 560 | { |
727 | jermar | 561 | int i; |
599 | jermar | 562 | ipl_t ipl; |
563 | entry_lo_t lo0, lo1; |
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704 | jermar | 564 | entry_hi_t hi, hi_save; |
598 | jermar | 565 | tlb_index_t index; |
566 | |||
599 | jermar | 567 | ASSERT(asid != ASID_INVALID); |
568 | |||
704 | jermar | 569 | hi_save.value = cp0_entry_hi_read(); |
599 | jermar | 570 | ipl = interrupts_disable(); |
571 | |||
983 | palkovsky | 572 | for (i = 0; i < cnt+1; i+=2) { |
727 | jermar | 573 | hi.value = 0; |
574 | prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); |
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575 | cp0_entry_hi_write(hi.value); |
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599 | jermar | 576 | |
727 | jermar | 577 | tlbp(); |
578 | index.value = cp0_index_read(); |
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598 | jermar | 579 | |
727 | jermar | 580 | if (!index.p) { |
581 | /* Entry was found, index register contains valid index. */ |
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582 | tlbr(); |
||
599 | jermar | 583 | |
727 | jermar | 584 | lo0.value = cp0_entry_lo0_read(); |
585 | lo1.value = cp0_entry_lo1_read(); |
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599 | jermar | 586 | |
727 | jermar | 587 | lo0.v = 0; |
588 | lo1.v = 0; |
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599 | jermar | 589 | |
727 | jermar | 590 | cp0_entry_lo0_write(lo0.value); |
591 | cp0_entry_lo1_write(lo1.value); |
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599 | jermar | 592 | |
727 | jermar | 593 | tlbwi(); |
594 | } |
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598 | jermar | 595 | } |
599 | jermar | 596 | |
597 | interrupts_restore(ipl); |
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704 | jermar | 598 | cp0_entry_hi_write(hi_save.value); |
598 | jermar | 599 | } |