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/*
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 * Copyright (C) 2003-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <interrupt.h>
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#include <arch/interrupt.h>
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#include <arch/types.h>
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#include <arch.h>
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#include <arch/cp0.h>
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#include <time/clock.h>
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#include <arch/drivers/arc.h>
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/** Disable interrupts.
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 *
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 * @return Old interrupt priority level.
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 */
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ipl_t interrupts_disable(void)
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{
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    ipl_t ipl = (ipl_t) cp0_status_read();
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    cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
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    return ipl;
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}
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/** Enable interrupts.
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 *
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 * @return Old interrupt priority level.
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 */
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ipl_t interrupts_enable(void)
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{
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    ipl_t ipl = (ipl_t) cp0_status_read();
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    cp0_status_write(ipl | cp0_status_ie_enabled_bit);
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    return ipl;
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}
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/** Restore interrupt priority level.
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 *
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 * @param ipl Saved interrupt priority level.
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 */
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void interrupts_restore(ipl_t ipl)
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{
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    cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
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}
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/** Read interrupt priority level.
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 *
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 * @return Current interrupt priority level.
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 */
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ipl_t interrupts_read(void)
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{
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    return cp0_status_read();
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}
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static void timer_exception(int n, void *stack)
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{
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    cp0_compare_write(cp0_count_read() + cp0_compare_value);
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    clock();
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}
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static void swint0(int n, void *stack)
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{
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    cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
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}
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static void swint1(int n, void *stack)
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{
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    cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
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}
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/* Initialize basic tables for exception dispatching */
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void interrupt_init(void)
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{
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    int i;
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    int_register(TIMER_IRQ, "timer", timer_exception);
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    int_register(0, "swint0", swint0);
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    int_register(1, "swint1", swint1);
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}