WebSVN – HelenOS – Blame – /trunk/kernel/arch/ia64/src/mm/tlb.c

Rev	Author	Line No.	Line
740	jermar	1	/*
		2	* Copyright (C) 2006 Jakub Jermar
		3	* All rights reserved.
		4	*
		5	* Redistribution and use in source and binary forms, with or without
		6	* modification, are permitted provided that the following conditions
		7	* are met:
		8	*
		9	* - Redistributions of source code must retain the above copyright
		10	* notice, this list of conditions and the following disclaimer.
		11	* - Redistributions in binary form must reproduce the above copyright
		12	* notice, this list of conditions and the following disclaimer in the
		13	* documentation and/or other materials provided with the distribution.
		14	* - The name of the author may not be used to endorse or promote products
		15	* derived from this software without specific prior written permission.
		16	*
		17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
		18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
		19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
		20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
		21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
		22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
		23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
		24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
		26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		27	*/
		28
		29	/*
		30	* TLB management.
		31	*/
		32
		33	#include <mm/tlb.h>
818	vana	34	#include <arch/mm/tlb.h>
819	vana	35	#include <arch/barrier.h>
740	jermar	36
818	vana	37
756	jermar	38	/** Invalidate all TLB entries. */
740	jermar	39	void tlb_invalidate_all(void)
		40	{
		41	/* TODO */
		42	}
		43
		44	/** Invalidate entries belonging to an address space.
		45	*
		46	* @param asid Address space identifier.
		47	*/
		48	void tlb_invalidate_asid(asid_t asid)
		49	{
		50	/* TODO */
		51	}
818	vana	52
		53
		54
819	vana	55	void tlb_fill_data(__address va,asid_t asid,tlb_entry_t entry)
818	vana	56	{
		57	region_register rr;
		58
		59
		60	if(!(entry.not_present.p)) return;
		61
		62	rr.word=rr_read(VA_REGION(va));
		63
		64	if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
		65	{
819	vana	66	asm volatile
818	vana	67	(
		68	"srlz.i;;\n"
		69	"srlz.d;;\n"
		70	"mov r8=psr;;\n"
		71	"and r9=r8,%0;;\n" /(~PSR_IC_MASK)/
		72	"mov psr.l=r9;;\n"
		73	"srlz.d;;\n"
		74	"srlz.i;;\n"
819	vana	75	"mov cr.ifa=%1\n" /va/
		76	"mov cr.itir=%2;;\n" /entry.word[1]/
818	vana	77	"itc.d %3;;\n" /entry.word[0]/
		78	"mov psr.l=r8;;\n"
		79	"srlz.d;;\n"
		80	:
		81	:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
		82	:"r8","r9"
		83	);
		84	}
		85	else
		86	{
		87	region_register rr0;
		88	rr0=rr;
		89	rr0.map.rid=ASID2RID(asid,VA_REGION(va));
		90	rr_write(VA_REGION(va),rr0.word);
819	vana	91	srlz_d();
		92	asm volatile
818	vana	93	(
		94	"mov r8=psr;;\n"
		95	"and r9=r8,%0;;\n" /(~PSR_IC_MASK)/
		96	"mov psr.l=r9;;\n"
		97	"srlz.d;;\n"
819	vana	98	"mov cr.ifa=%1\n" /va/
		99	"mov cr.itir=%2;;\n" /entry.word[1]/
818	vana	100	"itc.d %3;;\n" /entry.word[0]/
		101	"mov psr.l=r8;;\n"
		102	"srlz.d;;\n"
		103	:
		104	:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
		105	:"r8","r9"
		106	);
		107	rr_write(VA_REGION(va),rr.word);
		108	}
		109
		110
		111	}
		112
819	vana	113	void tlb_fill_code(__address va,asid_t asid,tlb_entry_t entry)
818	vana	114	{
		115	region_register rr;
		116
		117
		118	if(!(entry.not_present.p)) return;
		119
		120	rr.word=rr_read(VA_REGION(va));
		121
		122	if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
		123	{
819	vana	124	asm volatile
818	vana	125	(
		126	"srlz.i;;\n"
		127	"srlz.d;;\n"
		128	"mov r8=psr;;\n"
		129	"and r9=r8,%0;;\n" /(~PSR_IC_MASK)/
		130	"mov psr.l=r9;;\n"
		131	"srlz.d;;\n"
		132	"srlz.i;;\n"
819	vana	133	"mov cr.ifa=%1\n" /va/
		134	"mov cr.itir=%2;;\n" /entry.word[1]/
818	vana	135	"itc.i %3;;\n" /entry.word[0]/
		136	"mov psr.l=r8;;\n"
		137	"srlz.d;;\n"
		138	:
		139	:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
		140	:"r8","r9"
		141	);
		142	}
		143	else
		144	{
		145	region_register rr0;
		146	rr0=rr;
		147	rr0.map.rid=ASID2RID(asid,VA_REGION(va));
		148	rr_write(VA_REGION(va),rr0.word);
819	vana	149	srlz_d();
		150	asm volatile
818	vana	151	(
		152	"mov r8=psr;;\n"
		153	"and r9=r8,%0;;\n" /(~PSR_IC_MASK)/
		154	"mov psr.l=r9;;\n"
		155	"srlz.d;;\n"
819	vana	156	"mov cr.ifa=%1\n" /va/
		157	"mov cr.itir=%2;;\n" /entry.word[1]/
818	vana	158	"itc.i %3;;\n" /entry.word[0]/
		159	"mov psr.l=r8;;\n"
		160	"srlz.d;;\n"
		161	:
		162	:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
		163	:"r8","r9"
		164	);
		165	rr_write(VA_REGION(va),rr.word);
		166	}
		167
		168
		169	}
		170
		171
819	vana	172	void tlb_fill_data_tr(__u64 tr,__address va,asid_t asid,tlb_entry_t entry)
		173	{
		174	region_register rr;
		175
		176
		177	if(!(entry.not_present.p)) return;
		178
		179	rr.word=rr_read(VA_REGION(va));
		180
		181	if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
		182	{
		183	asm volatile
		184	(
		185	"srlz.i;;\n"
		186	"srlz.d;;\n"
		187	"mov r8=psr;;\n"
		188	"and r9=r8,%0;;\n" /(~PSR_IC_MASK)/
		189	"mov psr.l=r9;;\n"
		190	"srlz.d;;\n"
		191	"srlz.i;;\n"
		192	"mov cr.ifa=%1\n" /va/
		193	"mov cr.itir=%2;;\n" /entry.word[1]/
		194	"itr.d dtr[%4]=%3;;\n" /entry.word[0]/
		195	"mov psr.l=r8;;\n"
		196	"srlz.d;;\n"
		197	:
		198	:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]),"r"(tr)
		199	:"r8","r9"
		200	);
		201	}
		202	else
		203	{
		204	region_register rr0;
		205	rr0=rr;
		206	rr0.map.rid=ASID2RID(asid,VA_REGION(va));
		207	rr_write(VA_REGION(va),rr0.word);
		208	srlz_d();
		209	asm volatile
		210	(
		211	"mov r8=psr;;\n"
		212	"and r9=r8,%0;;\n" /(~PSR_IC_MASK)/
		213	"mov psr.l=r9;;\n"
		214	"srlz.d;;\n"
		215	"mov cr.ifa=%1\n" /va/
		216	"mov cr.itir=%2;;\n" /entry.word[1]/
		217	"itr.d dtr[%4]=%3;;\n" /entry.word[0]/
		218	"mov psr.l=r8;;\n"
		219	"srlz.d;;\n"
		220	:
		221	:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]),"r"(tr)
		222	:"r8","r9"
		223	);
		224	rr_write(VA_REGION(va),rr.word);
		225	}
		226
		227
		228	}
		229
		230	void tlb_fill_code_tr(__u64 tr,__address va,asid_t asid,tlb_entry_t entry)
		231	{
		232	region_register rr;
		233
		234
		235	if(!(entry.not_present.p)) return;
		236
		237	rr.word=rr_read(VA_REGION(va));
		238
		239	if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
		240	{
		241	asm volatile
		242	(
		243	"srlz.i;;\n"
		244	"srlz.d;;\n"
		245	"mov r8=psr;;\n"
		246	"and r9=r8,%0;;\n" /(~PSR_IC_MASK)/
		247	"mov psr.l=r9;;\n"
		248	"srlz.d;;\n"
		249	"srlz.i;;\n"
		250	"mov cr.ifa=%1\n" /va/
		251	"mov cr.itir=%2;;\n" /entry.word[1]/
		252	"itr.i itr[%4]=%3;;\n" /entry.word[0]/
		253	"mov psr.l=r8;;\n"
		254	"srlz.d;;\n"
		255	:
		256	:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]),"r"(tr)
		257	:"r8","r9"
		258	);
		259	}
		260	else
		261	{
		262	region_register rr0;
		263	rr0=rr;
		264	rr0.map.rid=ASID2RID(asid,VA_REGION(va));
		265	rr_write(VA_REGION(va),rr0.word);
		266	srlz_d();
		267	asm volatile
		268	(
		269	"mov r8=psr;;\n"
		270	"and r9=r8,%0;;\n" /(~PSR_IC_MASK)/
		271	"mov psr.l=r9;;\n"
		272	"srlz.d;;\n"
		273	"mov cr.ifa=%1\n" /va/
		274	"mov cr.itir=%2;;\n" /entry.word[1]/
		275	"itr.i itr[%4]=%3;;\n" /entry.word[0]/
		276	"mov psr.l=r8;;\n"
		277	"srlz.d;;\n"
		278	:
		279	:"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]),"r"(tr)
		280	:"r8","r9"
		281	);
		282	rr_write(VA_REGION(va),rr.word);
		283	}
		284
		285
		286	}
		287

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