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432 | jermar | 1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #ifndef __ia64_REGISTER_H__ |
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30 | #define __ia64_REGISTER_H__ |
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31 | |||
32 | #include <arch/types.h> |
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33 | |||
34 | #define CR_IVR_MASK 0xf |
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35 | #define PSR_I_MASK 0x4000 |
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36 | |||
470 | jermar | 37 | /** Application registers. */ |
38 | #define AR_KR0 0 |
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39 | #define AR_KR1 1 |
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40 | #define AR_KR2 2 |
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41 | #define AR_KR3 3 |
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42 | #define AR_KR4 4 |
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43 | #define AR_KR5 5 |
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44 | #define AR_KR6 6 |
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45 | #define AR_KR7 7 |
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46 | /* AR 8-15 reserved */ |
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47 | #define AR_RSC 16 |
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48 | #define AR_BSP 17 |
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49 | #define AR_BSPSTORE 18 |
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50 | #define AR_RNAT 19 |
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51 | /* AR 20 reserved */ |
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52 | #define AR_FCR 21 |
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53 | /* AR 22-23 reserved */ |
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54 | #define AR_EFLAG 24 |
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55 | #define AR_CSD 25 |
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56 | #define AR_SSD 26 |
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57 | #define AR_CFLG 27 |
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58 | #define AR_FSR 28 |
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59 | #define AR_FIR 29 |
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60 | #define AR_FDR 30 |
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61 | /* AR 31 reserved */ |
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62 | #define AR_CCV 32 |
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63 | /* AR 33-35 reserved */ |
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64 | #define AR_UNAT 36 |
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65 | /* AR 37-39 reserved */ |
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66 | #define AR_FPSR 40 |
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67 | /* AR 41-43 reserved */ |
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68 | #define AR_ITC 44 |
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69 | /* AR 45-47 reserved */ |
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70 | /* AR 48-63 ignored */ |
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71 | #define AR_PFS 64 |
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72 | #define AR_LC 65 |
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73 | #define AR_EC 66 |
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74 | /* AR 67-111 reserved */ |
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75 | /* AR 112-127 ignored */ |
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76 | |||
77 | /** Control registers. */ |
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78 | #define CR_DCR 0 |
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79 | #define CR_ITM 1 |
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80 | #define CR_IVA 2 |
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81 | /* CR3-CR7 reserved */ |
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82 | #define CR_PTA 8 |
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83 | /* CR9-CR15 reserved */ |
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84 | #define CR_IPSR 16 |
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85 | #define CR_ISR 17 |
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86 | /* CR18 reserved */ |
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87 | #define CR_IIP 19 |
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88 | #define CR_IFA 20 |
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89 | #define CR_ITIR 21 |
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90 | #define CR_IIPA 22 |
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91 | #define CR_IFS 23 |
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92 | #define CR_IIM 24 |
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93 | #define CR_IHA 25 |
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94 | /* CR26-CR63 reserved */ |
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95 | #define CR_LID 64 |
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96 | #define CR_IVR 65 |
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97 | #define CR_TPR 66 |
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98 | #define CR_EOI 67 |
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99 | #define CR_IRR0 68 |
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100 | #define CR_IRR1 69 |
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101 | #define CR_IRR2 70 |
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102 | #define CR_IRR3 71 |
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103 | #define CR_ITV 72 |
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104 | #define CR_PMV 73 |
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105 | #define CR_CMCV 74 |
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106 | /* CR75-CR79 reserved */ |
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107 | #define CR_LRR0 80 |
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108 | #define CR_LRR1 81 |
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109 | /* CR82-CR127 reserved */ |
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110 | |||
433 | jermar | 111 | /** External Interrupt Vector Register */ |
112 | union cr_ivr { |
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113 | __u8 vector; |
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114 | __u64 value; |
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115 | }; |
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116 | |||
117 | typedef union cr_ivr cr_ivr_t; |
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118 | |||
119 | /** Task Priority Register */ |
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120 | union cr_tpr { |
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121 | struct { |
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122 | unsigned : 4; |
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123 | unsigned mic: 4; /**< Mask Interrupt Class. */ |
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124 | unsigned : 8; |
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125 | unsigned mmi: 1; /**< Mask Maskable Interrupts. */ |
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126 | } __attribute__ ((packed)); |
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127 | __u64 value; |
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128 | }; |
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129 | |||
130 | typedef union cr_tpr cr_tpr_t; |
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131 | |||
132 | /** Interval Timer Vector */ |
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133 | union cr_itv { |
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134 | struct { |
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135 | unsigned vector : 8; |
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136 | unsigned : 4; |
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137 | unsigned : 1; |
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138 | unsigned : 3; |
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139 | unsigned m : 1; /**< Mask. */ |
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140 | } __attribute__ ((packed)); |
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141 | __u64 value; |
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142 | }; |
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143 | |||
144 | typedef union cr_itv cr_itv_t; |
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145 | |||
432 | jermar | 146 | #endif |