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173 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
173 jermar 3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
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 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
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 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
1888 jermar 29
/** @addtogroup ia64   
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
1888 jermar 35
#ifndef KERN_ia64_ASM_H_
36
#define KERN_ia64_ASM_H_
173 jermar 37
 
747 jermar 38
#include <config.h>
173 jermar 39
#include <arch/types.h>
432 jermar 40
#include <arch/register.h>
173 jermar 41
 
2726 vana 42
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
2515 vana 43
 
3929 jermar 44
static inline void pio_write_8(ioport8_t *port, uint8_t v)
2515 vana 45
{
3929 jermar 46
    uintptr_t prt = (uintptr_t) port;
47
 
3774 jermar 48
    *((uint8_t *)(IA64_IOSPACE_ADDRESS +
3929 jermar 49
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
2726 vana 50
 
2515 vana 51
    asm volatile ("mf\n" ::: "memory");
52
}
53
 
3929 jermar 54
static inline void pio_write_16(ioport16_t *port, uint16_t v)
3490 vana 55
{
3929 jermar 56
    uintptr_t prt = (uintptr_t) port;
57
 
3774 jermar 58
    *((uint16_t *)(IA64_IOSPACE_ADDRESS +
3929 jermar 59
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
2515 vana 60
 
3490 vana 61
    asm volatile ("mf\n" ::: "memory");
62
}
63
 
3929 jermar 64
static inline void pio_write_32(ioport32_t *port, uint32_t v)
3490 vana 65
{
3929 jermar 66
    uintptr_t prt = (uintptr_t) port;
67
 
3774 jermar 68
    *((uint32_t *)(IA64_IOSPACE_ADDRESS +
3929 jermar 69
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
3490 vana 70
 
71
    asm volatile ("mf\n" ::: "memory");
72
}
73
 
3929 jermar 74
static inline uint8_t pio_read_8(ioport8_t *port)
2515 vana 75
{
3929 jermar 76
    uintptr_t prt = (uintptr_t) port;
77
 
2515 vana 78
    asm volatile ("mf\n" ::: "memory");
2726 vana 79
 
3774 jermar 80
    return *((uint8_t *)(IA64_IOSPACE_ADDRESS +
3929 jermar 81
        ((prt & 0xfff) | ((prt >> 2) << 12))));
2515 vana 82
}
83
 
3929 jermar 84
static inline uint16_t pio_read_16(ioport16_t *port)
3490 vana 85
{
3929 jermar 86
    uintptr_t prt = (uintptr_t) port;
87
 
3490 vana 88
    asm volatile ("mf\n" ::: "memory");
2515 vana 89
 
3774 jermar 90
    return *((uint16_t *)(IA64_IOSPACE_ADDRESS +
3929 jermar 91
        ((prt & 0xffE) | ((prt >> 2) << 12))));
3490 vana 92
}
2515 vana 93
 
3929 jermar 94
static inline uint32_t pio_read_32(ioport32_t *port)
3490 vana 95
{
3929 jermar 96
    uintptr_t prt = (uintptr_t) port;
97
 
3490 vana 98
    asm volatile ("mf\n" ::: "memory");
99
 
3774 jermar 100
    return *((uint32_t *)(IA64_IOSPACE_ADDRESS +
3929 jermar 101
        ((prt & 0xfff) | ((prt >> 2) << 12))));
3490 vana 102
}
103
 
180 jermar 104
/** Return base address of current stack
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 *
106
 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE long.
108
 * The stack must start on page boundary.
109
 */
1780 jermar 110
static inline uintptr_t get_stack_base(void)
173 jermar 111
{
1780 jermar 112
    uint64_t v;
180 jermar 113
 
3577 vana 114
    //I'm not sure why but this code bad inlines in scheduler, 
115
    //so THE shifts about 16B and causes kernel panic
116
    //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
117
    //return v;
180 jermar 118
 
3577 vana 119
    //this code have the same meaning but inlines well
120
    asm volatile ("mov %0 = r12" : "=r" (v)  );
121
    return v & (~(STACK_SIZE-1));
173 jermar 122
}
123
 
919 jermar 124
/** Return Processor State Register.
125
 *
126
 * @return PSR.
127
 */
1780 jermar 128
static inline uint64_t psr_read(void)
919 jermar 129
{
1780 jermar 130
    uint64_t v;
919 jermar 131
 
2082 decky 132
    asm volatile ("mov %0 = psr\n" : "=r" (v));
919 jermar 133
 
134
    return v;
135
}
136
 
470 jermar 137
/** Read IVA (Interruption Vector Address).
138
 *
139
 * @return Return location of interruption vector table.
140
 */
1780 jermar 141
static inline uint64_t iva_read(void)
470 jermar 142
{
1780 jermar 143
    uint64_t v;
470 jermar 144
 
2082 decky 145
    asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
470 jermar 146
 
147
    return v;
148
}
149
 
150
/** Write IVA (Interruption Vector Address) register.
151
 *
1708 jermar 152
 * @param v New location of interruption vector table.
470 jermar 153
 */
1780 jermar 154
static inline void iva_write(uint64_t v)
470 jermar 155
{
2082 decky 156
    asm volatile ("mov cr.iva = %0\n" : : "r" (v));
470 jermar 157
}
158
 
159
 
432 jermar 160
/** Read IVR (External Interrupt Vector Register).
431 jermar 161
 *
162
 * @return Highest priority, pending, unmasked external interrupt vector.
163
 */
1780 jermar 164
static inline uint64_t ivr_read(void)
431 jermar 165
{
1780 jermar 166
    uint64_t v;
431 jermar 167
 
2082 decky 168
    asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
431 jermar 169
 
432 jermar 170
    return v;
431 jermar 171
}
195 vana 172
 
3577 vana 173
static inline uint64_t cr64_read(void)
174
{
175
    uint64_t v;
176
 
177
    asm volatile ("mov %0 = cr64\n" : "=r" (v));
178
 
179
    return v;
180
}
181
 
182
 
432 jermar 183
/** Write ITC (Interval Timer Counter) register.
184
 *
1708 jermar 185
 * @param v New counter value.
432 jermar 186
 */
1780 jermar 187
static inline void itc_write(uint64_t v)
432 jermar 188
{
2082 decky 189
    asm volatile ("mov ar.itc = %0\n" : : "r" (v));
432 jermar 190
}
431 jermar 191
 
432 jermar 192
/** Read ITC (Interval Timer Counter) register.
193
 *
194
 * @return Current counter value.
195
 */
1780 jermar 196
static inline uint64_t itc_read(void)
432 jermar 197
{
1780 jermar 198
    uint64_t v;
432 jermar 199
 
2082 decky 200
    asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
432 jermar 201
 
202
    return v;
203
}
195 vana 204
 
432 jermar 205
/** Write ITM (Interval Timer Match) register.
206
 *
1708 jermar 207
 * @param v New match value.
432 jermar 208
 */
1780 jermar 209
static inline void itm_write(uint64_t v)
432 jermar 210
{
2082 decky 211
    asm volatile ("mov cr.itm = %0\n" : : "r" (v));
432 jermar 212
}
195 vana 213
 
1488 vana 214
/** Read ITM (Interval Timer Match) register.
215
 *
216
 * @return Match value.
217
 */
1780 jermar 218
static inline uint64_t itm_read(void)
1488 vana 219
{
1780 jermar 220
    uint64_t v;
1488 vana 221
 
2082 decky 222
    asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
1488 vana 223
 
224
    return v;
225
}
226
 
433 jermar 227
/** Read ITV (Interval Timer Vector) register.
228
 *
229
 * @return Current vector and mask bit.
230
 */
1780 jermar 231
static inline uint64_t itv_read(void)
433 jermar 232
{
1780 jermar 233
    uint64_t v;
433 jermar 234
 
2082 decky 235
    asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
433 jermar 236
 
237
    return v;
238
}
239
 
432 jermar 240
/** Write ITV (Interval Timer Vector) register.
241
 *
1708 jermar 242
 * @param v New vector and mask bit.
432 jermar 243
 */
1780 jermar 244
static inline void itv_write(uint64_t v)
432 jermar 245
{
2082 decky 246
    asm volatile ("mov cr.itv = %0\n" : : "r" (v));
432 jermar 247
}
238 vana 248
 
432 jermar 249
/** Write EOI (End Of Interrupt) register.
250
 *
1708 jermar 251
 * @param v This value is ignored.
432 jermar 252
 */
1780 jermar 253
static inline void eoi_write(uint64_t v)
432 jermar 254
{
2082 decky 255
    asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
432 jermar 256
}
257
 
258
/** Read TPR (Task Priority Register).
259
 *
260
 * @return Current value of TPR.
261
 */
1780 jermar 262
static inline uint64_t tpr_read(void)
432 jermar 263
{
1780 jermar 264
    uint64_t v;
432 jermar 265
 
2082 decky 266
    asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
432 jermar 267
 
268
    return v;
269
}
270
 
271
/** Write TPR (Task Priority Register).
272
 *
1708 jermar 273
 * @param v New value of TPR.
432 jermar 274
 */
1780 jermar 275
static inline void tpr_write(uint64_t v)
432 jermar 276
{
2082 decky 277
    asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
432 jermar 278
}
279
 
280
/** Disable interrupts.
281
 *
282
 * Disable interrupts and return previous
283
 * value of PSR.
284
 *
285
 * @return Old interrupt priority level.
286
 */
287
static ipl_t interrupts_disable(void)
288
{
1780 jermar 289
    uint64_t v;
432 jermar 290
 
2082 decky 291
    asm volatile (
432 jermar 292
        "mov %0 = psr\n"
293
        "rsm %1\n"
294
        : "=r" (v)
295
        : "i" (PSR_I_MASK)
296
    );
297
 
298
    return (ipl_t) v;
299
}
300
 
301
/** Enable interrupts.
302
 *
303
 * Enable interrupts and return previous
304
 * value of PSR.
305
 *
306
 * @return Old interrupt priority level.
307
 */
308
static ipl_t interrupts_enable(void)
309
{
1780 jermar 310
    uint64_t v;
432 jermar 311
 
2082 decky 312
    asm volatile (
432 jermar 313
        "mov %0 = psr\n"
314
        "ssm %1\n"
315
        ";;\n"
316
        "srlz.d\n"
317
        : "=r" (v)
318
        : "i" (PSR_I_MASK)
319
    );
320
 
321
    return (ipl_t) v;
322
}
323
 
324
/** Restore interrupt priority level.
325
 *
326
 * Restore PSR.
327
 *
328
 * @param ipl Saved interrupt priority level.
329
 */
330
static inline void interrupts_restore(ipl_t ipl)
331
{
472 jermar 332
    if (ipl & PSR_I_MASK)
333
        (void) interrupts_enable();
334
    else
335
        (void) interrupts_disable();
432 jermar 336
}
337
 
338
/** Return interrupt priority level.
339
 *
340
 * @return PSR.
341
 */
342
static inline ipl_t interrupts_read(void)
343
{
919 jermar 344
    return (ipl_t) psr_read();
432 jermar 345
}
346
 
746 jermar 347
/** Disable protection key checking. */
348
static inline void pk_disable(void)
349
{
2082 decky 350
    asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
746 jermar 351
}
352
 
432 jermar 353
extern void cpu_halt(void);
354
extern void cpu_sleep(void);
1780 jermar 355
extern void asm_delay_loop(uint32_t t);
238 vana 356
 
3774 jermar 357
extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
358
    uint64_t, uint64_t);
919 jermar 359
 
173 jermar 360
#endif
1702 cejka 361
 
1888 jermar 362
/** @}
1702 cejka 363
 */