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1816 | decky | 1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
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3 | * Copyright (C) 2005 Sergey Bondari |
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1840 | decky | 4 | * Copyright (C) 2006 Martin Decky |
1816 | decky | 5 | * All rights reserved. |
6 | * |
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7 | * Redistribution and use in source and binary forms, with or without |
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8 | * modification, are permitted provided that the following conditions |
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9 | * are met: |
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10 | * |
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11 | * - Redistributions of source code must retain the above copyright |
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12 | * notice, this list of conditions and the following disclaimer. |
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13 | * - Redistributions in binary form must reproduce the above copyright |
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14 | * notice, this list of conditions and the following disclaimer in the |
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15 | * documentation and/or other materials provided with the distribution. |
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16 | * - The name of the author may not be used to endorse or promote products |
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17 | * derived from this software without specific prior written permission. |
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18 | * |
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19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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20 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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21 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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22 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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24 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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25 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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26 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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28 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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29 | */ |
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30 | |||
31 | /** @addtogroup xen32 |
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32 | * @{ |
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33 | */ |
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34 | /** @file |
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35 | */ |
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36 | |||
1888 | jermar | 37 | #ifndef KERN_xen32_ASM_H_ |
38 | #define KERN_xen32_ASM_H_ |
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1816 | decky | 39 | |
40 | #include <arch/pm.h> |
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41 | #include <arch/types.h> |
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1830 | decky | 42 | #include <arch/barrier.h> |
1816 | decky | 43 | #include <config.h> |
44 | |||
45 | extern void enable_l_apic_in_msr(void); |
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46 | |||
47 | |||
48 | extern void asm_delay_loop(uint32_t t); |
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49 | extern void asm_fake_loop(uint32_t t); |
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50 | |||
51 | |||
52 | /** Halt CPU |
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53 | * |
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54 | * Halt the current CPU until interrupt event. |
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55 | */ |
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1828 | decky | 56 | #define cpu_halt() ((void) 0) |
57 | #define cpu_sleep() ((void) 0) |
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1816 | decky | 58 | |
59 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
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60 | { \ |
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61 | unative_t res; \ |
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62 | __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
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63 | return res; \ |
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64 | } |
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65 | |||
66 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
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67 | { \ |
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68 | __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
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69 | } |
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70 | |||
71 | GEN_READ_REG(cr0); |
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72 | GEN_READ_REG(cr2); |
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73 | |||
74 | GEN_READ_REG(dr0); |
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75 | GEN_READ_REG(dr1); |
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76 | GEN_READ_REG(dr2); |
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77 | GEN_READ_REG(dr3); |
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78 | GEN_READ_REG(dr6); |
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79 | GEN_READ_REG(dr7); |
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80 | |||
81 | GEN_WRITE_REG(dr0); |
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82 | GEN_WRITE_REG(dr1); |
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83 | GEN_WRITE_REG(dr2); |
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84 | GEN_WRITE_REG(dr3); |
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85 | GEN_WRITE_REG(dr6); |
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86 | GEN_WRITE_REG(dr7); |
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87 | |||
88 | /** Byte to port |
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89 | * |
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90 | * Output byte to port |
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91 | * |
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92 | * @param port Port to write to |
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93 | * @param val Value to write |
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94 | */ |
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95 | static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
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96 | |||
97 | /** Word to port |
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98 | * |
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99 | * Output word to port |
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100 | * |
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101 | * @param port Port to write to |
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102 | * @param val Value to write |
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103 | */ |
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104 | static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
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105 | |||
106 | /** Double word to port |
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107 | * |
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108 | * Output double word to port |
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109 | * |
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110 | * @param port Port to write to |
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111 | * @param val Value to write |
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112 | */ |
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113 | static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
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114 | |||
115 | /** Byte from port |
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116 | * |
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117 | * Get byte from port |
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118 | * |
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119 | * @param port Port to read from |
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120 | * @return Value read |
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121 | */ |
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122 | static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
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123 | |||
124 | /** Word from port |
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125 | * |
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126 | * Get word from port |
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127 | * |
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128 | * @param port Port to read from |
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129 | * @return Value read |
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130 | */ |
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131 | static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
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132 | |||
133 | /** Double word from port |
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134 | * |
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135 | * Get double word from port |
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136 | * |
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137 | * @param port Port to read from |
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138 | * @return Value read |
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139 | */ |
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140 | static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
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141 | |||
142 | /** Enable interrupts. |
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143 | * |
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144 | * Enable interrupts and return previous |
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145 | * value of EFLAGS. |
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146 | * |
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147 | * @return Old interrupt priority level. |
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148 | */ |
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149 | static inline ipl_t interrupts_enable(void) |
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150 | { |
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1830 | decky | 151 | // FIXME SMP |
152 | |||
153 | ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask; |
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154 | write_barrier(); |
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155 | shared_info.vcpu_info[0].evtchn_upcall_mask = 0; |
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156 | write_barrier(); |
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157 | if (shared_info.vcpu_info[0].evtchn_upcall_pending) |
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158 | force_evtchn_callback(); |
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159 | |||
1816 | decky | 160 | return v; |
161 | } |
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162 | |||
163 | /** Disable interrupts. |
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164 | * |
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165 | * Disable interrupts and return previous |
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166 | * value of EFLAGS. |
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167 | * |
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168 | * @return Old interrupt priority level. |
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169 | */ |
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170 | static inline ipl_t interrupts_disable(void) |
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171 | { |
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1830 | decky | 172 | // FIXME SMP |
173 | |||
174 | ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask; |
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175 | shared_info.vcpu_info[0].evtchn_upcall_mask = 1; |
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176 | write_barrier(); |
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177 | |||
1816 | decky | 178 | return v; |
179 | } |
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180 | |||
181 | /** Restore interrupt priority level. |
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182 | * |
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183 | * Restore EFLAGS. |
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184 | * |
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185 | * @param ipl Saved interrupt priority level. |
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186 | */ |
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187 | static inline void interrupts_restore(ipl_t ipl) |
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188 | { |
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1830 | decky | 189 | if (ipl == 0) |
190 | interrupts_enable(); |
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191 | else |
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192 | interrupts_disable(); |
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1816 | decky | 193 | } |
194 | |||
195 | /** Return interrupt priority level. |
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196 | * |
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197 | * @return EFLAFS. |
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198 | */ |
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199 | static inline ipl_t interrupts_read(void) |
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200 | { |
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1830 | decky | 201 | // FIXME SMP |
202 | |||
203 | return shared_info.vcpu_info[0].evtchn_upcall_mask; |
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1816 | decky | 204 | } |
205 | |||
206 | /** Return base address of current stack |
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207 | * |
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208 | * Return the base address of the current stack. |
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209 | * The stack is assumed to be STACK_SIZE bytes long. |
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210 | * The stack must start on page boundary. |
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211 | */ |
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212 | static inline uintptr_t get_stack_base(void) |
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213 | { |
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214 | uintptr_t v; |
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215 | |||
216 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
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217 | |||
218 | return v; |
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219 | } |
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220 | |||
221 | static inline uint64_t rdtsc(void) |
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222 | { |
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223 | uint64_t v; |
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224 | |||
225 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
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226 | |||
227 | return v; |
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228 | } |
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229 | |||
230 | /** Return current IP address */ |
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231 | static inline uintptr_t * get_ip() |
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232 | { |
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233 | uintptr_t *ip; |
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234 | |||
235 | __asm__ volatile ( |
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236 | "mov %%eip, %0" |
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237 | : "=r" (ip) |
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238 | ); |
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239 | return ip; |
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240 | } |
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241 | |||
242 | /** Invalidate TLB Entry. |
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243 | * |
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244 | * @param addr Address on a page whose TLB entry is to be invalidated. |
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245 | */ |
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246 | static inline void invlpg(uintptr_t addr) |
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247 | { |
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248 | __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
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249 | } |
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250 | |||
251 | /** Load GDTR register from memory. |
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252 | * |
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253 | * @param gdtr_reg Address of memory from where to load GDTR. |
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254 | */ |
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255 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
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256 | { |
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257 | __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
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258 | } |
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259 | |||
260 | /** Store GDTR register to memory. |
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261 | * |
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262 | * @param gdtr_reg Address of memory to where to load GDTR. |
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263 | */ |
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264 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
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265 | { |
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266 | __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
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267 | } |
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268 | |||
269 | /** Load TR from descriptor table. |
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270 | * |
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271 | * @param sel Selector specifying descriptor of TSS segment. |
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272 | */ |
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273 | static inline void tr_load(uint16_t sel) |
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274 | { |
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275 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
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276 | } |
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277 | |||
278 | #endif |
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279 | |||
280 | /** @} |
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281 | */ |