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1816 | decky | 1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
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3 | * Copyright (C) 2005 Sergey Bondari |
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4 | * All rights reserved. |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * |
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10 | * - Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * - Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * - The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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28 | */ |
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29 | |||
30 | /** @addtogroup xen32 |
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31 | * @{ |
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32 | */ |
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33 | /** @file |
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34 | */ |
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35 | |||
36 | #ifndef __xen32_ASM_H__ |
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37 | #define __xen32_ASM_H__ |
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38 | |||
39 | #include <arch/pm.h> |
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40 | #include <arch/types.h> |
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41 | #include <config.h> |
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42 | |||
43 | extern uint32_t interrupt_handler_size; |
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44 | |||
45 | extern void interrupt_handlers(void); |
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46 | |||
47 | extern void enable_l_apic_in_msr(void); |
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48 | |||
49 | |||
50 | extern void asm_delay_loop(uint32_t t); |
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51 | extern void asm_fake_loop(uint32_t t); |
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52 | |||
53 | |||
54 | /** Halt CPU |
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55 | * |
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56 | * Halt the current CPU until interrupt event. |
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57 | */ |
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1828 | decky | 58 | #define cpu_halt() ((void) 0) |
59 | #define cpu_sleep() ((void) 0) |
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1816 | decky | 60 | |
61 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
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62 | { \ |
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63 | unative_t res; \ |
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64 | __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
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65 | return res; \ |
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66 | } |
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67 | |||
68 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
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69 | { \ |
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70 | __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
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71 | } |
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72 | |||
73 | GEN_READ_REG(cr0); |
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74 | GEN_READ_REG(cr2); |
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75 | |||
76 | GEN_READ_REG(dr0); |
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77 | GEN_READ_REG(dr1); |
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78 | GEN_READ_REG(dr2); |
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79 | GEN_READ_REG(dr3); |
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80 | GEN_READ_REG(dr6); |
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81 | GEN_READ_REG(dr7); |
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82 | |||
83 | GEN_WRITE_REG(dr0); |
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84 | GEN_WRITE_REG(dr1); |
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85 | GEN_WRITE_REG(dr2); |
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86 | GEN_WRITE_REG(dr3); |
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87 | GEN_WRITE_REG(dr6); |
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88 | GEN_WRITE_REG(dr7); |
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89 | |||
90 | /** Byte to port |
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91 | * |
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92 | * Output byte to port |
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93 | * |
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94 | * @param port Port to write to |
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95 | * @param val Value to write |
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96 | */ |
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97 | static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
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98 | |||
99 | /** Word to port |
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100 | * |
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101 | * Output word to port |
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102 | * |
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103 | * @param port Port to write to |
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104 | * @param val Value to write |
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105 | */ |
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106 | static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
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107 | |||
108 | /** Double word to port |
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109 | * |
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110 | * Output double word to port |
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111 | * |
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112 | * @param port Port to write to |
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113 | * @param val Value to write |
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114 | */ |
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115 | static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
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116 | |||
117 | /** Byte from port |
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118 | * |
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119 | * Get byte from port |
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120 | * |
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121 | * @param port Port to read from |
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122 | * @return Value read |
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123 | */ |
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124 | static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
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125 | |||
126 | /** Word from port |
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127 | * |
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128 | * Get word from port |
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129 | * |
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130 | * @param port Port to read from |
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131 | * @return Value read |
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132 | */ |
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133 | static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
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134 | |||
135 | /** Double word from port |
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136 | * |
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137 | * Get double word from port |
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138 | * |
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139 | * @param port Port to read from |
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140 | * @return Value read |
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141 | */ |
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142 | static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
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143 | |||
144 | /** Enable interrupts. |
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145 | * |
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146 | * Enable interrupts and return previous |
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147 | * value of EFLAGS. |
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148 | * |
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149 | * @return Old interrupt priority level. |
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150 | */ |
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151 | static inline ipl_t interrupts_enable(void) |
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152 | { |
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1817 | decky | 153 | ipl_t v = 0; |
154 | /* __asm__ volatile ( |
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1816 | decky | 155 | "pushf\n\t" |
156 | "popl %0\n\t" |
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157 | "sti\n" |
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158 | : "=r" (v) |
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1817 | decky | 159 | );*/ |
1816 | decky | 160 | return v; |
161 | } |
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162 | |||
163 | /** Disable interrupts. |
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164 | * |
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165 | * Disable interrupts and return previous |
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166 | * value of EFLAGS. |
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167 | * |
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168 | * @return Old interrupt priority level. |
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169 | */ |
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170 | static inline ipl_t interrupts_disable(void) |
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171 | { |
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1817 | decky | 172 | ipl_t v = 0; |
173 | /* __asm__ volatile ( |
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1816 | decky | 174 | "pushf\n\t" |
175 | "popl %0\n\t" |
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176 | "cli\n" |
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177 | : "=r" (v) |
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1817 | decky | 178 | );*/ |
1816 | decky | 179 | return v; |
180 | } |
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181 | |||
182 | /** Restore interrupt priority level. |
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183 | * |
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184 | * Restore EFLAGS. |
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185 | * |
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186 | * @param ipl Saved interrupt priority level. |
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187 | */ |
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188 | static inline void interrupts_restore(ipl_t ipl) |
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189 | { |
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1817 | decky | 190 | /* __asm__ volatile ( |
1816 | decky | 191 | "pushl %0\n\t" |
192 | "popf\n" |
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193 | : : "r" (ipl) |
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1817 | decky | 194 | );*/ |
1816 | decky | 195 | } |
196 | |||
197 | /** Return interrupt priority level. |
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198 | * |
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199 | * @return EFLAFS. |
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200 | */ |
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201 | static inline ipl_t interrupts_read(void) |
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202 | { |
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1817 | decky | 203 | ipl_t v = 0; |
204 | /* __asm__ volatile ( |
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1816 | decky | 205 | "pushf\n\t" |
206 | "popl %0\n" |
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207 | : "=r" (v) |
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1817 | decky | 208 | );*/ |
1816 | decky | 209 | return v; |
210 | } |
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211 | |||
212 | /** Return base address of current stack |
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213 | * |
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214 | * Return the base address of the current stack. |
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215 | * The stack is assumed to be STACK_SIZE bytes long. |
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216 | * The stack must start on page boundary. |
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217 | */ |
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218 | static inline uintptr_t get_stack_base(void) |
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219 | { |
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220 | uintptr_t v; |
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221 | |||
222 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
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223 | |||
224 | return v; |
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225 | } |
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226 | |||
227 | static inline uint64_t rdtsc(void) |
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228 | { |
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229 | uint64_t v; |
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230 | |||
231 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
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232 | |||
233 | return v; |
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234 | } |
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235 | |||
236 | /** Return current IP address */ |
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237 | static inline uintptr_t * get_ip() |
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238 | { |
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239 | uintptr_t *ip; |
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240 | |||
241 | __asm__ volatile ( |
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242 | "mov %%eip, %0" |
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243 | : "=r" (ip) |
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244 | ); |
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245 | return ip; |
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246 | } |
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247 | |||
248 | /** Invalidate TLB Entry. |
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249 | * |
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250 | * @param addr Address on a page whose TLB entry is to be invalidated. |
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251 | */ |
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252 | static inline void invlpg(uintptr_t addr) |
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253 | { |
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254 | __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
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255 | } |
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256 | |||
257 | /** Load GDTR register from memory. |
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258 | * |
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259 | * @param gdtr_reg Address of memory from where to load GDTR. |
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260 | */ |
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261 | static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
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262 | { |
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263 | __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
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264 | } |
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265 | |||
266 | /** Store GDTR register to memory. |
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267 | * |
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268 | * @param gdtr_reg Address of memory to where to load GDTR. |
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269 | */ |
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270 | static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
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271 | { |
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272 | __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
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273 | } |
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274 | |||
275 | /** Load TR from descriptor table. |
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276 | * |
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277 | * @param sel Selector specifying descriptor of TSS segment. |
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278 | */ |
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279 | static inline void tr_load(uint16_t sel) |
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280 | { |
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281 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
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282 | } |
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283 | |||
284 | #endif |
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285 | |||
286 | /** @} |
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287 | */ |