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1 | jermar | 1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #include <arch/types.h> |
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11 | jermar | 30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
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32 | #include <arch/smp/mp.h> |
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1 | jermar | 33 | #include <mm/page.h> |
34 | #include <time/delay.h> |
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35 | #include <arch/interrupt.h> |
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36 | #include <print.h> |
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37 | #include <arch/asm.h> |
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38 | #include <arch.h> |
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39 | |||
16 | jermar | 40 | #ifdef __SMP__ |
41 | |||
1 | jermar | 42 | /* |
43 | * This is functional, far-from-general-enough interface to the APIC. |
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44 | * Advanced Programmable Interrupt Controller for MP systems. |
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45 | * Tested on: |
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46 | * Bochs 2.0.2 with 2-8 CPUs |
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47 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
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48 | */ |
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49 | |||
50 | /* |
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51 | * These variables either stay configured as initilalized, or are changed by |
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52 | * the MP configuration code. |
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53 | * |
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54 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
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55 | * optimize the code too much and accesses to l_apic and io_apic, that must |
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56 | * always be 32-bit, would use byte oriented instructions. |
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57 | */ |
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58 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
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59 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
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60 | |||
61 | __u32 apic_id_mask = 0; |
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62 | |||
63 | int apic_poll_errors(void); |
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64 | |||
65 | void apic_init(void) |
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66 | { |
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67 | __u32 tmp, id, i; |
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68 | |||
69 | trap_register(VECTOR_APIC_SPUR, apic_spurious); |
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70 | |||
71 | enable_irqs_function = io_apic_enable_irqs; |
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72 | disable_irqs_function = io_apic_disable_irqs; |
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73 | eoi_function = l_apic_eoi; |
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74 | |||
75 | /* |
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76 | * Configure interrupt routing. |
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77 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
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78 | * Other interrupts will be forwarded to the lowest priority CPU. |
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79 | */ |
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80 | io_apic_disable_irqs(0xffff); |
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81 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
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82 | for (i=1; i<16; i++) { |
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83 | int pin; |
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84 | |||
85 | if ((pin = mp_irq_to_pin(i)) != -1) |
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86 | io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI); |
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87 | } |
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88 | |||
89 | |||
90 | /* |
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91 | * Ensure that io_apic has unique ID. |
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92 | */ |
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93 | tmp = io_apic_read(IOAPICID); |
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94 | id = (tmp >> 24) & 0xf; |
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95 | if ((1<<id) & apic_id_mask) { |
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96 | int i; |
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97 | |||
98 | for (i=0; i<15; i++) { |
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99 | if (!((1<<i) & apic_id_mask)) { |
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100 | io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24)); |
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101 | break; |
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102 | } |
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103 | } |
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104 | } |
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105 | |||
106 | |||
107 | |||
108 | /* |
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109 | * Configure the BSP's lapic. |
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110 | */ |
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111 | l_apic_init(); |
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112 | l_apic_debug(); |
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113 | } |
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114 | |||
115 | void apic_spurious(__u8 n, __u32 stack[]) |
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116 | { |
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15 | jermar | 117 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
1 | jermar | 118 | } |
119 | |||
120 | int apic_poll_errors(void) |
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121 | { |
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122 | __u32 esr; |
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123 | |||
124 | esr = l_apic[ESR] & ~ESRClear; |
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125 | |||
126 | if ((esr>>0) & 1) |
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127 | printf("Send CS Error\n"); |
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128 | if ((esr>>1) & 1) |
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129 | printf("Receive CS Error\n"); |
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130 | if ((esr>>2) & 1) |
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131 | printf("Send Accept Error\n"); |
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132 | if ((esr>>3) & 1) |
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133 | printf("Receive Accept Error\n"); |
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134 | if ((esr>>5) & 1) |
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135 | printf("Send Illegal Vector\n"); |
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136 | if ((esr>>6) & 1) |
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137 | printf("Received Illegal Vector\n"); |
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138 | if ((esr>>7) & 1) |
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139 | printf("Illegal Register Address\n"); |
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140 | |||
141 | return !esr; |
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142 | } |
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143 | |||
144 | /* |
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15 | jermar | 145 | * Send all CPUs excluding CPU IPI vector. |
5 | jermar | 146 | */ |
147 | int l_apic_broadcast_custom_ipi(__u8 vector) |
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148 | { |
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149 | __u32 lo; |
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150 | |||
151 | /* |
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152 | * Read the ICR register in and zero all non-reserved fields. |
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153 | */ |
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154 | lo = l_apic[ICRlo] & ICRloClear; |
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155 | |||
156 | lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector; |
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157 | |||
158 | l_apic[ICRlo] = lo; |
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159 | |||
160 | lo = l_apic[ICRlo] & ICRloClear; |
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161 | if (lo & SEND_PENDING) |
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162 | printf("IPI is pending.\n"); |
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163 | |||
164 | return apic_poll_errors(); |
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165 | } |
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166 | |||
167 | /* |
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1 | jermar | 168 | * Universal Start-up Algorithm for bringing up the AP processors. |
169 | */ |
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170 | int l_apic_send_init_ipi(__u8 apicid) |
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171 | { |
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172 | __u32 lo, hi; |
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173 | int i; |
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174 | |||
175 | /* |
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176 | * Read the ICR register in and zero all non-reserved fields. |
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177 | */ |
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178 | lo = l_apic[ICRlo] & ICRloClear; |
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179 | hi = l_apic[ICRhi] & ICRhiClear; |
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180 | |||
181 | lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
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182 | hi |= apicid << 24; |
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183 | |||
184 | l_apic[ICRhi] = hi; |
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185 | l_apic[ICRlo] = lo; |
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186 | |||
187 | /* |
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188 | * According to MP Specification, 20us should be enough to |
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189 | * deliver the IPI. |
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190 | */ |
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191 | delay(20); |
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192 | |||
193 | if (!apic_poll_errors()) return 0; |
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194 | |||
195 | lo = l_apic[ICRlo] & ICRloClear; |
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196 | if (lo & SEND_PENDING) |
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197 | printf("IPI is pending.\n"); |
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198 | |||
199 | l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
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200 | |||
201 | /* |
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202 | * Wait 10ms as MP Specification specifies. |
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203 | */ |
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204 | delay(10000); |
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205 | |||
206 | /* |
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207 | * MP specification says this should not be done for 82489DX-based |
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208 | * l_apic's. However, everything is ok as long as STARTUP IPI is ignored |
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209 | * by 8249DX. |
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210 | */ |
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211 | for (i = 0; i < 2; i++) { |
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212 | lo = l_apic[ICRlo] & ICRloClear; |
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213 | lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
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214 | l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
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215 | delay(200); |
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216 | } |
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217 | |||
218 | return apic_poll_errors(); |
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219 | } |
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220 | |||
221 | void l_apic_init(void) |
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222 | { |
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223 | __u32 tmp, t1, t2; |
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16 | jermar | 224 | int cpu_id = config.cpu_active - 1; |
1 | jermar | 225 | |
226 | |||
16 | jermar | 227 | /* |
228 | * Here we set local APIC ID's so that they match operating system's CPU ID's |
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229 | * This operation is dangerous as it is model specific. |
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230 | * TODO: some care should be taken. |
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231 | * NOTE: CPU may not be used to define APIC ID |
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232 | */ |
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233 | if (l_apic_id() != cpu_id) { |
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234 | l_apic[L_APIC_ID] &= L_APIC_IDClear; |
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235 | l_apic[L_APIC_ID] |= (l_apic[L_APIC_ID]&L_APIC_IDClear)|((cpu_id)<<L_APIC_IDShift); |
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236 | } |
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237 | |||
1 | jermar | 238 | l_apic[LVT_Err] |= (1<<16); |
239 | l_apic[LVT_LINT0] |= (1<<16); |
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240 | l_apic[LVT_LINT1] |= (1<<16); |
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241 | |||
242 | tmp = l_apic[SVR] & SVRClear; |
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243 | l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR); |
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244 | |||
245 | l_apic[TPR] &= TPRClear; |
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246 | |||
15 | jermar | 247 | if (CPU->arch.family >= 6) |
1 | jermar | 248 | enable_l_apic_in_msr(); |
249 | |||
250 | tmp = l_apic[ICRlo] & ICRloClear; |
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251 | l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL; |
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252 | |||
253 | /* |
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254 | * Program the timer for periodic mode and respective vector. |
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255 | */ |
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256 | |||
257 | l_apic[TDCR] &= TDCRClear; |
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258 | l_apic[TDCR] |= 0xb; |
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259 | tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK); |
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260 | l_apic[LVT_Tm] = tmp & ~(1<<16); |
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261 | |||
262 | t1 = l_apic[CCRT]; |
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263 | l_apic[ICRT] = 0xffffffff; |
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264 | |||
265 | while (l_apic[CCRT] == t1) |
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266 | ; |
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267 | |||
268 | t1 = l_apic[CCRT]; |
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269 | delay(1000); |
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270 | t2 = l_apic[CCRT]; |
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271 | |||
272 | l_apic[ICRT] = t1-t2; |
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273 | } |
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274 | |||
275 | void l_apic_eoi(void) |
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276 | { |
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277 | l_apic[EOI] = 0; |
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278 | } |
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279 | |||
280 | void l_apic_debug(void) |
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281 | { |
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282 | #ifdef LAPIC_VERBOSE |
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283 | int i, lint; |
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284 | |||
16 | jermar | 285 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
1 | jermar | 286 | |
287 | printf("LVT_Tm: "); |
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288 | if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(','); |
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289 | if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
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290 | if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
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291 | printf("%B\n", l_apic[LVT_Tm] & 0xff); |
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292 | |||
293 | for (i=0; i<2; i++) { |
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294 | lint = i ? LVT_LINT1 : LVT_LINT0; |
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295 | printf("LVT_LINT%d: ", i); |
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296 | if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
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297 | if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(','); |
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298 | printf("%d", l_apic[lint] & (1<<14)); putchar(','); |
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299 | printf("%d", l_apic[lint] & (1<<13)); putchar(','); |
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300 | if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
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301 | |||
302 | switch ((l_apic[lint]>>8)&7) { |
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303 | case 0: printf("fixed"); break; |
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304 | case 4: printf("NMI"); break; |
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305 | case 7: printf("ExtINT"); break; |
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306 | } |
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307 | putchar(','); |
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308 | printf("%B\n", l_apic[lint] & 0xff); |
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309 | } |
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310 | |||
311 | printf("LVT_Err: "); |
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312 | if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
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313 | if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
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314 | printf("%B\n", l_apic[LVT_Err] & 0xff); |
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315 | |||
316 | /* |
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317 | * This register is supported only on P6 and higher. |
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318 | */ |
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16 | jermar | 319 | if (CPU->arch.family > 5) { |
1 | jermar | 320 | printf("LVT_PCINT: "); |
321 | if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
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322 | if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
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323 | switch ((l_apic[LVT_PCINT] >> 8)&7) { |
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324 | case 0: printf("fixed"); break; |
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325 | case 4: printf("NMI"); break; |
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326 | case 7: printf("ExtINT"); break; |
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327 | } |
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328 | putchar(','); |
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329 | printf("%B\n", l_apic[LVT_PCINT] & 0xff); |
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330 | } |
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331 | #endif |
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332 | } |
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333 | |||
334 | void l_apic_timer_interrupt(__u8 n, __u32 stack[]) |
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335 | { |
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336 | l_apic_eoi(); |
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337 | clock(); |
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338 | } |
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339 | |||
16 | jermar | 340 | __u8 l_apic_id(void) |
341 | { |
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342 | return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask; |
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343 | } |
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344 | |||
1 | jermar | 345 | __u32 io_apic_read(__u8 address) |
346 | { |
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347 | __u32 tmp; |
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348 | |||
349 | tmp = io_apic[IOREGSEL] & ~0xf; |
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350 | io_apic[IOREGSEL] = tmp | address; |
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351 | return io_apic[IOWIN]; |
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352 | } |
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353 | |||
354 | void io_apic_write(__u8 address, __u32 x) |
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355 | { |
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356 | __u32 tmp; |
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357 | |||
358 | tmp = io_apic[IOREGSEL] & ~0xf; |
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359 | io_apic[IOREGSEL] = tmp | address; |
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360 | io_apic[IOWIN] = x; |
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361 | } |
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362 | |||
363 | void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags) |
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364 | { |
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365 | __u32 reglo, reghi; |
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366 | int dlvr = 0; |
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367 | |||
368 | if (flags & LOPRI) |
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369 | dlvr = 1; |
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370 | |||
371 | reglo = io_apic_read(IOREDTBL + signal*2); |
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372 | reghi = io_apic_read(IOREDTBL + signal*2 + 1); |
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373 | |||
374 | reghi &= ~0x0f000000; |
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375 | reghi |= (dest<<24); |
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376 | |||
377 | reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */ |
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378 | reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v; |
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379 | |||
380 | io_apic_write(IOREDTBL + signal*2, reglo); |
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381 | io_apic_write(IOREDTBL + signal*2 + 1, reghi); |
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382 | } |
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383 | |||
384 | void io_apic_disable_irqs(__u16 irqmask) |
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385 | { |
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386 | int i,pin; |
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387 | __u32 reglo; |
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388 | |||
389 | for (i=0;i<16;i++) { |
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390 | if ((irqmask>>i) & 1) { |
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391 | /* |
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392 | * Mask the signal input in IO APIC if there is a |
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393 | * mapping for the respective IRQ number. |
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394 | */ |
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395 | pin = mp_irq_to_pin(i); |
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396 | if (pin != -1) { |
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397 | reglo = io_apic_read(IOREDTBL + pin*2); |
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398 | reglo |= (1<<16); |
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399 | io_apic_write(IOREDTBL + pin*2,reglo); |
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400 | } |
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401 | |||
402 | } |
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403 | } |
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404 | } |
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405 | |||
406 | void io_apic_enable_irqs(__u16 irqmask) |
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407 | { |
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408 | int i,pin; |
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409 | __u32 reglo; |
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410 | |||
411 | for (i=0;i<16;i++) { |
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412 | if ((irqmask>>i) & 1) { |
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413 | /* |
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414 | * Unmask the signal input in IO APIC if there is a |
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415 | * mapping for the respective IRQ number. |
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416 | */ |
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417 | pin = mp_irq_to_pin(i); |
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418 | if (pin != -1) { |
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419 | reglo = io_apic_read(IOREDTBL + pin*2); |
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420 | reglo &= ~(1<<16); |
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421 | io_apic_write(IOREDTBL + pin*2,reglo); |
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422 | } |
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423 | |||
424 | } |
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425 | } |
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426 | |||
427 | } |
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428 | |||
429 | #endif /* __SMP__ */ |