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1 | jermar | 1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #include <arch/types.h> |
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11 | jermar | 30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
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32 | #include <arch/smp/mp.h> |
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1 | jermar | 33 | #include <mm/page.h> |
34 | #include <time/delay.h> |
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35 | #include <arch/interrupt.h> |
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36 | #include <print.h> |
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37 | #include <arch/asm.h> |
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38 | #include <arch.h> |
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39 | |||
16 | jermar | 40 | #ifdef __SMP__ |
41 | |||
1 | jermar | 42 | /* |
43 | * This is functional, far-from-general-enough interface to the APIC. |
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44 | * Advanced Programmable Interrupt Controller for MP systems. |
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45 | * Tested on: |
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46 | * Bochs 2.0.2 with 2-8 CPUs |
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47 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
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48 | */ |
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49 | |||
50 | /* |
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51 | * These variables either stay configured as initilalized, or are changed by |
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52 | * the MP configuration code. |
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53 | * |
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54 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
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55 | * optimize the code too much and accesses to l_apic and io_apic, that must |
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56 | * always be 32-bit, would use byte oriented instructions. |
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57 | */ |
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58 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
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59 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
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60 | |||
61 | __u32 apic_id_mask = 0; |
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62 | |||
63 | int apic_poll_errors(void); |
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64 | |||
65 | void apic_init(void) |
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66 | { |
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67 | __u32 tmp, id, i; |
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68 | |||
69 | trap_register(VECTOR_APIC_SPUR, apic_spurious); |
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70 | |||
71 | enable_irqs_function = io_apic_enable_irqs; |
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72 | disable_irqs_function = io_apic_disable_irqs; |
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73 | eoi_function = l_apic_eoi; |
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74 | |||
75 | /* |
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76 | * Configure interrupt routing. |
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77 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
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78 | * Other interrupts will be forwarded to the lowest priority CPU. |
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79 | */ |
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80 | io_apic_disable_irqs(0xffff); |
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81 | trap_register(VECTOR_CLK, l_apic_timer_interrupt); |
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82 | for (i=1; i<16; i++) { |
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83 | int pin; |
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84 | |||
85 | if ((pin = mp_irq_to_pin(i)) != -1) |
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86 | io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI); |
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87 | } |
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88 | |||
89 | |||
90 | /* |
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91 | * Ensure that io_apic has unique ID. |
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92 | */ |
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93 | tmp = io_apic_read(IOAPICID); |
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94 | id = (tmp >> 24) & 0xf; |
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95 | if ((1<<id) & apic_id_mask) { |
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96 | int i; |
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97 | |||
98 | for (i=0; i<15; i++) { |
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99 | if (!((1<<i) & apic_id_mask)) { |
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100 | io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24)); |
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101 | break; |
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102 | } |
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103 | } |
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104 | } |
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105 | |||
106 | /* |
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107 | * Configure the BSP's lapic. |
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108 | */ |
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109 | l_apic_init(); |
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110 | l_apic_debug(); |
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111 | } |
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112 | |||
113 | void apic_spurious(__u8 n, __u32 stack[]) |
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114 | { |
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15 | jermar | 115 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
1 | jermar | 116 | } |
117 | |||
118 | int apic_poll_errors(void) |
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119 | { |
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120 | __u32 esr; |
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121 | |||
122 | esr = l_apic[ESR] & ~ESRClear; |
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123 | |||
124 | if ((esr>>0) & 1) |
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125 | printf("Send CS Error\n"); |
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126 | if ((esr>>1) & 1) |
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127 | printf("Receive CS Error\n"); |
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128 | if ((esr>>2) & 1) |
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129 | printf("Send Accept Error\n"); |
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130 | if ((esr>>3) & 1) |
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131 | printf("Receive Accept Error\n"); |
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132 | if ((esr>>5) & 1) |
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133 | printf("Send Illegal Vector\n"); |
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134 | if ((esr>>6) & 1) |
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135 | printf("Received Illegal Vector\n"); |
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136 | if ((esr>>7) & 1) |
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137 | printf("Illegal Register Address\n"); |
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138 | |||
139 | return !esr; |
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140 | } |
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141 | |||
142 | /* |
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15 | jermar | 143 | * Send all CPUs excluding CPU IPI vector. |
5 | jermar | 144 | */ |
145 | int l_apic_broadcast_custom_ipi(__u8 vector) |
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146 | { |
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147 | __u32 lo; |
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148 | |||
149 | /* |
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150 | * Read the ICR register in and zero all non-reserved fields. |
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151 | */ |
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152 | lo = l_apic[ICRlo] & ICRloClear; |
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153 | |||
154 | lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector; |
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155 | |||
156 | l_apic[ICRlo] = lo; |
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157 | |||
158 | lo = l_apic[ICRlo] & ICRloClear; |
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159 | if (lo & SEND_PENDING) |
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160 | printf("IPI is pending.\n"); |
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161 | |||
162 | return apic_poll_errors(); |
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163 | } |
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164 | |||
165 | /* |
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1 | jermar | 166 | * Universal Start-up Algorithm for bringing up the AP processors. |
167 | */ |
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168 | int l_apic_send_init_ipi(__u8 apicid) |
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169 | { |
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170 | __u32 lo, hi; |
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171 | int i; |
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172 | |||
173 | /* |
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174 | * Read the ICR register in and zero all non-reserved fields. |
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175 | */ |
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176 | lo = l_apic[ICRlo] & ICRloClear; |
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177 | hi = l_apic[ICRhi] & ICRhiClear; |
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178 | |||
179 | lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
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180 | hi |= apicid << 24; |
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181 | |||
182 | l_apic[ICRhi] = hi; |
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183 | l_apic[ICRlo] = lo; |
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27 | jermar | 184 | |
1 | jermar | 185 | /* |
186 | * According to MP Specification, 20us should be enough to |
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187 | * deliver the IPI. |
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188 | */ |
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189 | delay(20); |
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190 | |||
191 | if (!apic_poll_errors()) return 0; |
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192 | |||
193 | lo = l_apic[ICRlo] & ICRloClear; |
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194 | if (lo & SEND_PENDING) |
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195 | printf("IPI is pending.\n"); |
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27 | jermar | 196 | |
1 | jermar | 197 | l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
198 | |||
199 | /* |
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200 | * Wait 10ms as MP Specification specifies. |
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201 | */ |
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202 | delay(10000); |
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203 | |||
27 | jermar | 204 | if (!is_82489DX_apic(l_apic[LAVR])) { |
205 | /* |
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206 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
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207 | */ |
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208 | for (i = 0; i<2; i++) { |
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209 | lo = l_apic[ICRlo] & ICRloClear; |
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210 | lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
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211 | l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL; |
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212 | delay(200); |
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213 | } |
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1 | jermar | 214 | } |
215 | |||
27 | jermar | 216 | |
1 | jermar | 217 | return apic_poll_errors(); |
218 | } |
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219 | |||
220 | void l_apic_init(void) |
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221 | { |
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222 | __u32 tmp, t1, t2; |
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223 | |||
224 | l_apic[LVT_Err] |= (1<<16); |
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225 | l_apic[LVT_LINT0] |= (1<<16); |
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226 | l_apic[LVT_LINT1] |= (1<<16); |
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227 | |||
228 | tmp = l_apic[SVR] & SVRClear; |
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229 | l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR); |
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230 | |||
231 | l_apic[TPR] &= TPRClear; |
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232 | |||
27 | jermar | 233 | // if (CPU->arch.family >= 6) |
234 | // enable_l_apic_in_msr(); |
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1 | jermar | 235 | |
236 | tmp = l_apic[ICRlo] & ICRloClear; |
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237 | l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL; |
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238 | |||
239 | /* |
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240 | * Program the timer for periodic mode and respective vector. |
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241 | */ |
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242 | |||
243 | l_apic[TDCR] &= TDCRClear; |
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244 | l_apic[TDCR] |= 0xb; |
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245 | tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK); |
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246 | l_apic[LVT_Tm] = tmp & ~(1<<16); |
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247 | |||
248 | t1 = l_apic[CCRT]; |
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249 | l_apic[ICRT] = 0xffffffff; |
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250 | |||
251 | while (l_apic[CCRT] == t1) |
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252 | ; |
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253 | |||
254 | t1 = l_apic[CCRT]; |
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255 | delay(1000); |
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256 | t2 = l_apic[CCRT]; |
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257 | |||
258 | l_apic[ICRT] = t1-t2; |
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259 | } |
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260 | |||
261 | void l_apic_eoi(void) |
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262 | { |
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263 | l_apic[EOI] = 0; |
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264 | } |
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265 | |||
266 | void l_apic_debug(void) |
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267 | { |
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268 | #ifdef LAPIC_VERBOSE |
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269 | int i, lint; |
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270 | |||
16 | jermar | 271 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
1 | jermar | 272 | |
273 | printf("LVT_Tm: "); |
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274 | if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(','); |
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275 | if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
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276 | if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
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277 | printf("%B\n", l_apic[LVT_Tm] & 0xff); |
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278 | |||
279 | for (i=0; i<2; i++) { |
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280 | lint = i ? LVT_LINT1 : LVT_LINT0; |
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281 | printf("LVT_LINT%d: ", i); |
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282 | if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
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283 | if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(','); |
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284 | printf("%d", l_apic[lint] & (1<<14)); putchar(','); |
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285 | printf("%d", l_apic[lint] & (1<<13)); putchar(','); |
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286 | if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
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287 | |||
288 | switch ((l_apic[lint]>>8)&7) { |
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289 | case 0: printf("fixed"); break; |
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290 | case 4: printf("NMI"); break; |
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291 | case 7: printf("ExtINT"); break; |
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292 | } |
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293 | putchar(','); |
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294 | printf("%B\n", l_apic[lint] & 0xff); |
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295 | } |
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296 | |||
297 | printf("LVT_Err: "); |
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298 | if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
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299 | if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
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300 | printf("%B\n", l_apic[LVT_Err] & 0xff); |
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301 | |||
302 | /* |
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303 | * This register is supported only on P6 and higher. |
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304 | */ |
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16 | jermar | 305 | if (CPU->arch.family > 5) { |
1 | jermar | 306 | printf("LVT_PCINT: "); |
307 | if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); |
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308 | if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(','); |
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309 | switch ((l_apic[LVT_PCINT] >> 8)&7) { |
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310 | case 0: printf("fixed"); break; |
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311 | case 4: printf("NMI"); break; |
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312 | case 7: printf("ExtINT"); break; |
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313 | } |
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314 | putchar(','); |
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315 | printf("%B\n", l_apic[LVT_PCINT] & 0xff); |
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316 | } |
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317 | #endif |
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318 | } |
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319 | |||
320 | void l_apic_timer_interrupt(__u8 n, __u32 stack[]) |
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321 | { |
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322 | l_apic_eoi(); |
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323 | clock(); |
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324 | } |
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325 | |||
21 | jermar | 326 | inline __u8 l_apic_id(void) |
16 | jermar | 327 | { |
328 | return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask; |
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329 | } |
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330 | |||
1 | jermar | 331 | __u32 io_apic_read(__u8 address) |
332 | { |
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333 | __u32 tmp; |
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334 | |||
335 | tmp = io_apic[IOREGSEL] & ~0xf; |
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336 | io_apic[IOREGSEL] = tmp | address; |
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337 | return io_apic[IOWIN]; |
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338 | } |
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339 | |||
340 | void io_apic_write(__u8 address, __u32 x) |
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341 | { |
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342 | __u32 tmp; |
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343 | |||
344 | tmp = io_apic[IOREGSEL] & ~0xf; |
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345 | io_apic[IOREGSEL] = tmp | address; |
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346 | io_apic[IOWIN] = x; |
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347 | } |
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348 | |||
349 | void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags) |
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350 | { |
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351 | __u32 reglo, reghi; |
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352 | int dlvr = 0; |
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353 | |||
354 | if (flags & LOPRI) |
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355 | dlvr = 1; |
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356 | |||
357 | reglo = io_apic_read(IOREDTBL + signal*2); |
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358 | reghi = io_apic_read(IOREDTBL + signal*2 + 1); |
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359 | |||
360 | reghi &= ~0x0f000000; |
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361 | reghi |= (dest<<24); |
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362 | |||
363 | reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */ |
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364 | reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v; |
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365 | |||
366 | io_apic_write(IOREDTBL + signal*2, reglo); |
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367 | io_apic_write(IOREDTBL + signal*2 + 1, reghi); |
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368 | } |
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369 | |||
370 | void io_apic_disable_irqs(__u16 irqmask) |
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371 | { |
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372 | int i,pin; |
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373 | __u32 reglo; |
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374 | |||
375 | for (i=0;i<16;i++) { |
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376 | if ((irqmask>>i) & 1) { |
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377 | /* |
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378 | * Mask the signal input in IO APIC if there is a |
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379 | * mapping for the respective IRQ number. |
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380 | */ |
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381 | pin = mp_irq_to_pin(i); |
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382 | if (pin != -1) { |
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383 | reglo = io_apic_read(IOREDTBL + pin*2); |
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384 | reglo |= (1<<16); |
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385 | io_apic_write(IOREDTBL + pin*2,reglo); |
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386 | } |
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387 | |||
388 | } |
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389 | } |
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390 | } |
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391 | |||
392 | void io_apic_enable_irqs(__u16 irqmask) |
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393 | { |
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394 | int i,pin; |
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395 | __u32 reglo; |
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396 | |||
397 | for (i=0;i<16;i++) { |
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398 | if ((irqmask>>i) & 1) { |
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399 | /* |
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400 | * Unmask the signal input in IO APIC if there is a |
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401 | * mapping for the respective IRQ number. |
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402 | */ |
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403 | pin = mp_irq_to_pin(i); |
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404 | if (pin != -1) { |
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405 | reglo = io_apic_read(IOREDTBL + pin*2); |
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406 | reglo &= ~(1<<16); |
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407 | io_apic_write(IOREDTBL + pin*2,reglo); |
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408 | } |
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409 | |||
410 | } |
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411 | } |
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412 | |||
413 | } |
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414 | |||
415 | #endif /* __SMP__ */ |