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1 jermar 1
/*
2
 * Copyright (C) 2001-2004 Jakub Jermar
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
29
#include <arch/types.h>
11 jermar 30
#include <arch/smp/apic.h>
31
#include <arch/smp/ap.h>
34 jermar 32
#include <arch/smp/mps.h>
693 decky 33
#include <arch/boot/boot.h>
1 jermar 34
#include <mm/page.h>
35
#include <time/delay.h>
576 palkovsky 36
#include <interrupt.h>
1 jermar 37
#include <arch/interrupt.h>
38
#include <print.h>
39
#include <arch/asm.h>
40
#include <arch.h>
41
 
458 decky 42
#ifdef CONFIG_SMP
16 jermar 43
 
1 jermar 44
/*
512 jermar 45
 * Advanced Programmable Interrupt Controller for SMP systems.
1 jermar 46
 * Tested on:
750 jermar 47
 *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
523 jermar 48
 *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
516 jermar 49
 *  VMware Workstation 5.5 with 2 CPUs
812 jermar 50
 *  QEMU 0.8.0 with 2-15 CPUs
1 jermar 51
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
437 decky 52
 *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
53
 *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
1 jermar 54
 */
55
 
56
/*
57
 * These variables either stay configured as initilalized, or are changed by
58
 * the MP configuration code.
59
 *
60
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
61
 * optimize the code too much and accesses to l_apic and io_apic, that must
62
 * always be 32-bit, would use byte oriented instructions.
63
 */
64
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
65
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
66
 
67
__u32 apic_id_mask = 0;
68
 
514 jermar 69
static int apic_poll_errors(void);
1 jermar 70
 
515 jermar 71
#ifdef LAPIC_VERBOSE
514 jermar 72
static char *delmod_str[] = {
73
    "Fixed",
74
    "Lowest Priority",
75
    "SMI",
76
    "Reserved",
77
    "NMI",
78
    "INIT",
79
    "STARTUP",
80
    "ExtInt"
81
};
82
 
83
static char *destmod_str[] = {
84
    "Physical",
85
    "Logical"
86
};
87
 
88
static char *trigmod_str[] = {
89
    "Edge",
90
    "Level"
91
};
92
 
93
static char *mask_str[] = {
94
    "Unmasked",
95
    "Masked"
96
};
97
 
98
static char *delivs_str[] = {
99
    "Idle",
100
    "Send Pending"
101
};
102
 
103
static char *tm_mode_str[] = {
104
    "One-shot",
105
    "Periodic"
106
};
107
 
108
static char *intpol_str[] = {
109
    "Polarity High",
110
    "Polarity Low"
111
};
515 jermar 112
#endif /* LAPIC_VERBOSE */
514 jermar 113
 
576 palkovsky 114
 
958 jermar 115
static void apic_spurious(int n, istate_t *istate);
116
static void l_apic_timer_interrupt(int n, istate_t *istate);
576 palkovsky 117
 
513 jermar 118
/** Initialize APIC on BSP. */
1 jermar 119
void apic_init(void)
120
{
515 jermar 121
    io_apic_id_t idreg;
122
    int i;
1 jermar 123
 
958 jermar 124
    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
1 jermar 125
 
126
    enable_irqs_function = io_apic_enable_irqs;
127
    disable_irqs_function = io_apic_disable_irqs;
128
    eoi_function = l_apic_eoi;
129
 
130
    /*
131
     * Configure interrupt routing.
132
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
133
     * Other interrupts will be forwarded to the lowest priority CPU.
134
     */
135
    io_apic_disable_irqs(0xffff);
958 jermar 136
    exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
515 jermar 137
    for (i = 0; i < IRQ_COUNT; i++) {
1 jermar 138
        int pin;
139
 
512 jermar 140
        if ((pin = smp_irq_to_pin(i)) != -1) {
515 jermar 141
            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
512 jermar 142
        }
1 jermar 143
    }
144
 
145
    /*
146
     * Ensure that io_apic has unique ID.
147
     */
515 jermar 148
    idreg.value = io_apic_read(IOAPICID);
149
    if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
150
        for (i = 0; i < APIC_ID_COUNT; i++) {
1 jermar 151
            if (!((1<<i) & apic_id_mask)) {
515 jermar 152
                idreg.apic_id = i;
153
                io_apic_write(IOAPICID, idreg.value);
1 jermar 154
                break;
155
            }
156
        }
157
    }
158
 
159
    /*
160
     * Configure the BSP's lapic.
161
     */
162
    l_apic_init();
515 jermar 163
 
1 jermar 164
    l_apic_debug();
165
}
166
 
514 jermar 167
/** APIC spurious interrupt handler.
168
 *
169
 * @param n Interrupt vector.
170
 * @param stack Interrupted stack.
171
 */
958 jermar 172
void apic_spurious(int n, istate_t *istate)
1 jermar 173
{
1667 jermar 174
#ifdef CONFIG_DEBUG
15 jermar 175
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
1667 jermar 176
#endif
1 jermar 177
}
178
 
514 jermar 179
/** Poll for APIC errors.
180
 *
181
 * Examine Error Status Register and report all errors found.
182
 *
183
 * @return 0 on error, 1 on success.
184
 */
1 jermar 185
int apic_poll_errors(void)
186
{
514 jermar 187
    esr_t esr;
1 jermar 188
 
514 jermar 189
    esr.value = l_apic[ESR];
1 jermar 190
 
514 jermar 191
    if (esr.send_checksum_error)
515 jermar 192
        printf("Send Checksum Error\n");
514 jermar 193
    if (esr.receive_checksum_error)
515 jermar 194
        printf("Receive Checksum Error\n");
514 jermar 195
    if (esr.send_accept_error)
1 jermar 196
        printf("Send Accept Error\n");
514 jermar 197
    if (esr.receive_accept_error)
1 jermar 198
        printf("Receive Accept Error\n");
514 jermar 199
    if (esr.send_illegal_vector)
1 jermar 200
        printf("Send Illegal Vector\n");
514 jermar 201
    if (esr.received_illegal_vector)
1 jermar 202
        printf("Received Illegal Vector\n");
514 jermar 203
    if (esr.illegal_register_address)
1 jermar 204
        printf("Illegal Register Address\n");
125 jermar 205
 
514 jermar 206
    return !esr.err_bitmap;
1 jermar 207
}
208
 
514 jermar 209
/** Send all CPUs excluding CPU IPI vector.
210
 *
211
 * @param vector Interrupt vector to be sent.
212
 *
213
 * @return 0 on failure, 1 on success.
5 jermar 214
 */
215
int l_apic_broadcast_custom_ipi(__u8 vector)
216
{
513 jermar 217
    icr_t icr;
5 jermar 218
 
513 jermar 219
    icr.lo = l_apic[ICRlo];
220
    icr.delmod = DELMOD_FIXED;
221
    icr.destmod = DESTMOD_LOGIC;
222
    icr.level = LEVEL_ASSERT;
223
    icr.shorthand = SHORTHAND_ALL_EXCL;
224
    icr.trigger_mode = TRIGMOD_LEVEL;
225
    icr.vector = vector;
5 jermar 226
 
513 jermar 227
    l_apic[ICRlo] = icr.lo;
5 jermar 228
 
513 jermar 229
    icr.lo = l_apic[ICRlo];
515 jermar 230
    if (icr.delivs == DELIVS_PENDING)
5 jermar 231
        printf("IPI is pending.\n");
232
 
233
    return apic_poll_errors();
234
}
235
 
514 jermar 236
/** Universal Start-up Algorithm for bringing up the AP processors.
237
 *
238
 * @param apicid APIC ID of the processor to be brought up.
239
 *
240
 * @return 0 on failure, 1 on success.
1 jermar 241
 */
242
int l_apic_send_init_ipi(__u8 apicid)
243
{
513 jermar 244
    icr_t icr;
1 jermar 245
    int i;
246
 
247
    /*
248
     * Read the ICR register in and zero all non-reserved fields.
249
     */
513 jermar 250
    icr.lo = l_apic[ICRlo];
251
    icr.hi = l_apic[ICRhi];
1 jermar 252
 
513 jermar 253
    icr.delmod = DELMOD_INIT;
254
    icr.destmod = DESTMOD_PHYS;
255
    icr.level = LEVEL_ASSERT;
256
    icr.trigger_mode = TRIGMOD_LEVEL;
257
    icr.shorthand = SHORTHAND_NONE;
258
    icr.vector = 0;
259
    icr.dest = apicid;
1 jermar 260
 
513 jermar 261
    l_apic[ICRhi] = icr.hi;
262
    l_apic[ICRlo] = icr.lo;
27 jermar 263
 
1 jermar 264
    /*
265
     * According to MP Specification, 20us should be enough to
266
     * deliver the IPI.
267
     */
268
    delay(20);
269
 
270
    if (!apic_poll_errors()) return 0;
271
 
513 jermar 272
    icr.lo = l_apic[ICRlo];
515 jermar 273
    if (icr.delivs == DELIVS_PENDING)
1 jermar 274
        printf("IPI is pending.\n");
27 jermar 275
 
513 jermar 276
    icr.delmod = DELMOD_INIT;
277
    icr.destmod = DESTMOD_PHYS;
278
    icr.level = LEVEL_DEASSERT;
279
    icr.shorthand = SHORTHAND_NONE;
280
    icr.trigger_mode = TRIGMOD_LEVEL;
281
    icr.vector = 0;
282
    l_apic[ICRlo] = icr.lo;
1 jermar 283
 
284
    /*
285
     * Wait 10ms as MP Specification specifies.
286
     */
287
    delay(10000);
288
 
27 jermar 289
    if (!is_82489DX_apic(l_apic[LAVR])) {
290
        /*
291
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
292
         */
293
        for (i = 0; i<2; i++) {
513 jermar 294
            icr.lo = l_apic[ICRlo];
295
            icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
296
            icr.delmod = DELMOD_STARTUP;
297
            icr.destmod = DESTMOD_PHYS;
298
            icr.level = LEVEL_ASSERT;
299
            icr.shorthand = SHORTHAND_NONE;
300
            icr.trigger_mode = TRIGMOD_LEVEL;
301
            l_apic[ICRlo] = icr.lo;
27 jermar 302
            delay(200);
303
        }
1 jermar 304
    }
305
 
306
    return apic_poll_errors();
307
}
308
 
514 jermar 309
/** Initialize Local APIC. */
1 jermar 310
void l_apic_init(void)
311
{
513 jermar 312
    lvt_error_t error;
313
    lvt_lint_t lint;
750 jermar 314
    tpr_t tpr;
513 jermar 315
    svr_t svr;
514 jermar 316
    icr_t icr;
317
    tdcr_t tdcr;
513 jermar 318
    lvt_tm_t tm;
672 jermar 319
    ldr_t ldr;
320
    dfr_t dfr;
513 jermar 321
    __u32 t1, t2;
1 jermar 322
 
513 jermar 323
    /* Initialize LVT Error register. */
324
    error.value = l_apic[LVT_Err];
325
    error.masked = true;
326
    l_apic[LVT_Err] = error.value;
1 jermar 327
 
513 jermar 328
    /* Initialize LVT LINT0 register. */
329
    lint.value = l_apic[LVT_LINT0];
330
    lint.masked = true;
331
    l_apic[LVT_LINT0] = lint.value;
1 jermar 332
 
513 jermar 333
    /* Initialize LVT LINT1 register. */
334
    lint.value = l_apic[LVT_LINT1];
335
    lint.masked = true;
336
    l_apic[LVT_LINT1] = lint.value;
750 jermar 337
 
338
    /* Task Priority Register initialization. */
339
    tpr.value = l_apic[TPR];
340
    tpr.pri_sc = 0;
341
    tpr.pri = 0;
342
    l_apic[TPR] = tpr.value;
513 jermar 343
 
344
    /* Spurious-Interrupt Vector Register initialization. */
345
    svr.value = l_apic[SVR];
346
    svr.vector = VECTOR_APIC_SPUR;
347
    svr.lapic_enabled = true;
750 jermar 348
    svr.focus_checking = true;
513 jermar 349
    l_apic[SVR] = svr.value;
350
 
31 jermar 351
    if (CPU->arch.family >= 6)
352
        enable_l_apic_in_msr();
1 jermar 353
 
513 jermar 354
    /* Interrupt Command Register initialization. */
355
    icr.lo = l_apic[ICRlo];
356
    icr.delmod = DELMOD_INIT;
357
    icr.destmod = DESTMOD_PHYS;
358
    icr.level = LEVEL_DEASSERT;
359
    icr.shorthand = SHORTHAND_ALL_INCL;
360
    icr.trigger_mode = TRIGMOD_LEVEL;
361
    l_apic[ICRlo] = icr.lo;
1 jermar 362
 
514 jermar 363
    /* Timer Divide Configuration Register initialization. */
364
    tdcr.value = l_apic[TDCR];
365
    tdcr.div_value = DIVIDE_1;
366
    l_apic[TDCR] = tdcr.value;
1 jermar 367
 
514 jermar 368
    /* Program local timer. */
513 jermar 369
    tm.value = l_apic[LVT_Tm];
370
    tm.vector = VECTOR_CLK;
371
    tm.mode = TIMER_PERIODIC;
372
    tm.masked = false;
373
    l_apic[LVT_Tm] = tm.value;
374
 
1540 jermar 375
    /*
376
     * Measure and configure the timer to generate timer
377
     * interrupt with period 1s/HZ seconds.
378
     */
1 jermar 379
    t1 = l_apic[CCRT];
380
    l_apic[ICRT] = 0xffffffff;
381
 
382
    while (l_apic[CCRT] == t1)
383
        ;
384
 
385
    t1 = l_apic[CCRT];
1540 jermar 386
    delay(1000000/HZ);
1 jermar 387
    t2 = l_apic[CCRT];
388
 
389
    l_apic[ICRT] = t1-t2;
672 jermar 390
 
391
    /* Program Logical Destination Register. */
392
    ldr.value = l_apic[LDR];
393
    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
394
        ldr.id = (1<<CPU->id);
395
    l_apic[LDR] = ldr.value;
396
 
397
    /* Program Destination Format Register for Flat mode. */
398
    dfr.value = l_apic[DFR];
399
    dfr.model = MODEL_FLAT;
400
    l_apic[DFR] = dfr.value;
1 jermar 401
}
402
 
514 jermar 403
/** Local APIC End of Interrupt. */
1 jermar 404
void l_apic_eoi(void)
405
{
406
    l_apic[EOI] = 0;
407
}
408
 
514 jermar 409
/** Dump content of Local APIC registers. */
1 jermar 410
void l_apic_debug(void)
411
{
412
#ifdef LAPIC_VERBOSE
514 jermar 413
    lvt_tm_t tm;
414
    lvt_lint_t lint;
415
    lvt_error_t error; 
416
 
16 jermar 417
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
1 jermar 418
 
514 jermar 419
    tm.value = l_apic[LVT_Tm];
1196 cejka 420
    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
514 jermar 421
    lint.value = l_apic[LVT_LINT0];
1196 cejka 422
    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
514 jermar 423
    lint.value = l_apic[LVT_LINT1];
1196 cejka 424
    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
514 jermar 425
    error.value = l_apic[LVT_Err];
1196 cejka 426
    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
1 jermar 427
#endif
428
}
429
 
514 jermar 430
/** Local APIC Timer Interrupt.
431
 *
432
 * @param n Interrupt vector number.
433
 * @param stack Interrupted stack.
434
 */
958 jermar 435
void l_apic_timer_interrupt(int n, istate_t *istate)
1 jermar 436
{
437
    l_apic_eoi();
438
    clock();
439
}
440
 
514 jermar 441
/** Get Local APIC ID.
442
 *
443
 * @return Local APIC ID.
444
 */
81 jermar 445
__u8 l_apic_id(void)
16 jermar 446
{
515 jermar 447
    l_apic_id_t idreg;
514 jermar 448
 
515 jermar 449
    idreg.value = l_apic[L_APIC_ID];
450
    return idreg.apic_id;
16 jermar 451
}
452
 
514 jermar 453
/** Read from IO APIC register.
454
 *
455
 * @param address IO APIC register address.
456
 *
457
 * @return Content of the addressed IO APIC register.
458
 */
1 jermar 459
__u32 io_apic_read(__u8 address)
460
{
514 jermar 461
    io_regsel_t regsel;
1 jermar 462
 
514 jermar 463
    regsel.value = io_apic[IOREGSEL];
464
    regsel.reg_addr = address;
465
    io_apic[IOREGSEL] = regsel.value;
1 jermar 466
    return io_apic[IOWIN];
467
}
468
 
514 jermar 469
/** Write to IO APIC register.
470
 *
471
 * @param address IO APIC register address.
472
 * @param Content to be written to the addressed IO APIC register.
473
 */
1 jermar 474
void io_apic_write(__u8 address, __u32 x)
475
{
514 jermar 476
    io_regsel_t regsel;
477
 
478
    regsel.value = io_apic[IOREGSEL];
479
    regsel.reg_addr = address;
480
    io_apic[IOREGSEL] = regsel.value;
1 jermar 481
    io_apic[IOWIN] = x;
482
}
483
 
514 jermar 484
/** Change some attributes of one item in I/O Redirection Table.
485
 *
486
 * @param pin IO APIC pin number.
487
 * @param dest Interrupt destination address.
488
 * @param v Interrupt vector to trigger.
489
 * @param flags Flags.
490
 */
491
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
1 jermar 492
{
512 jermar 493
    io_redirection_reg_t reg;
514 jermar 494
    int dlvr = DELMOD_FIXED;
1 jermar 495
 
496
    if (flags & LOPRI)
512 jermar 497
        dlvr = DELMOD_LOWPRI;
498
 
514 jermar 499
    reg.lo = io_apic_read(IOREDTBL + pin*2);
500
    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
1 jermar 501
 
672 jermar 502
    reg.dest = dest;
512 jermar 503
    reg.destmod = DESTMOD_LOGIC;
504
    reg.trigger_mode = TRIGMOD_EDGE;
505
    reg.intpol = POLARITY_HIGH;
506
    reg.delmod = dlvr;
507
    reg.intvec = v;
1 jermar 508
 
514 jermar 509
    io_apic_write(IOREDTBL + pin*2, reg.lo);
510
    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
1 jermar 511
}
512
 
514 jermar 513
/** Mask IRQs in IO APIC.
514
 *
515
 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
516
 */
1 jermar 517
void io_apic_disable_irqs(__u16 irqmask)
518
{
512 jermar 519
    io_redirection_reg_t reg;
520
    int i, pin;
1 jermar 521
 
522
    for (i=0;i<16;i++) {
515 jermar 523
        if (irqmask & (1<<i)) {
1 jermar 524
            /*
525
             * Mask the signal input in IO APIC if there is a
526
             * mapping for the respective IRQ number.
527
             */
512 jermar 528
            pin = smp_irq_to_pin(i);
1 jermar 529
            if (pin != -1) {
512 jermar 530
                reg.lo = io_apic_read(IOREDTBL + pin*2);
531
                reg.masked = true;
532
                io_apic_write(IOREDTBL + pin*2, reg.lo);
1 jermar 533
            }
534
 
535
        }
536
    }
537
}
538
 
514 jermar 539
/** Unmask IRQs in IO APIC.
540
 *
541
 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
542
 */
1 jermar 543
void io_apic_enable_irqs(__u16 irqmask)
544
{
512 jermar 545
    int i, pin;
546
    io_redirection_reg_t reg;  
1 jermar 547
 
548
    for (i=0;i<16;i++) {
515 jermar 549
        if (irqmask & (1<<i)) {
1 jermar 550
            /*
551
             * Unmask the signal input in IO APIC if there is a
552
             * mapping for the respective IRQ number.
553
             */
512 jermar 554
            pin = smp_irq_to_pin(i);
1 jermar 555
            if (pin != -1) {
512 jermar 556
                reg.lo = io_apic_read(IOREDTBL + pin*2);
557
                reg.masked = false;
558
                io_apic_write(IOREDTBL + pin*2, reg.lo);
1 jermar 559
            }
560
 
561
        }
562
    }
563
}
564
 
458 decky 565
#endif /* CONFIG_SMP */