WebSVN – HelenOS – Blame – /trunk/kernel/arch/ia32/src/pm.c

Rev	Author	Line No.	Line
1	jermar	1	/*
		2	* Copyright (C) 2001-2004 Jakub Jermar
		3	* All rights reserved.
		4	*
		5	* Redistribution and use in source and binary forms, with or without
		6	* modification, are permitted provided that the following conditions
		7	* are met:
		8	*
		9	* - Redistributions of source code must retain the above copyright
		10	* notice, this list of conditions and the following disclaimer.
		11	* - Redistributions in binary form must reproduce the above copyright
		12	* notice, this list of conditions and the following disclaimer in the
		13	* documentation and/or other materials provided with the distribution.
		14	* - The name of the author may not be used to endorse or promote products
		15	* derived from this software without specific prior written permission.
		16	*
		17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
		18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
		19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
		20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
		21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
		22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
		23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
		24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
		26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		27	*/
		28
		29	#include <arch/pm.h>
		30	#include <config.h>
		31	#include <arch/types.h>
		32	#include <typedefs.h>
		33	#include <arch/interrupt.h>
		34	#include <arch/asm.h>
		35	#include <arch/context.h>
		36	#include <panic.h>
		37
		38	/*
11	jermar	39	* Early ia32 configuration functions and data structures.
1	jermar	40	*/
		41
		42	/*
		43	* We have no use for segmentation so we set up flat mode. In this
		44	* mode, we use, for each privilege level, two segments spanning the
		45	* whole memory. One is for code and one is for data.
		46	*/
		47	struct descriptor gdt[GDT_ITEMS] = {
		48	/* NULL descriptor */
		49	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
		50	/* KTEXT descriptor */
		51	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
		52	/* KDATA descriptor */
		53	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
		54	/* UTEXT descriptor */
		55	{ 0xffff, 0, 0, AR_PRESENT \| AR_CODE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
		56	/* UDATA descriptor */
		57	{ 0xffff, 0, 0, AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER, 0xf, 0, 0, 1, 1, 0 },
		58	/* TSS descriptor - set up will be completed later */
		59	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
		60	};
		61
		62	static struct idescriptor idt[IDT_ITEMS];
		63
		64	static struct tss tss;
		65
		66	struct tss *tss_p = NULL;
		67
		68	/* gdtr changes everytime new CPU is initialized */
16	jermar	69	struct ptr_16_32 gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = (__address) gdt };
1	jermar	70	struct ptr_16_32 idtr = { .limit = sizeof(idt), .base = (__address) idt };
		71
		72	void gdt_setbase(struct descriptor *d, __address base)
		73	{
		74	d->base_0_15 = base & 0xffff;
		75	d->base_16_23 = (base >> 16) & 0xff;
		76	d->base_24_31 = (base >> 24) & 0xff;
		77	}
		78
		79	void gdt_setlimit(struct descriptor *d, __address limit)
		80	{
		81	d->limit_0_15 = limit & 0xffff;
		82	d->limit_16_19 = (limit >> 16) & 0xf;
		83	}
		84
		85	void idt_setoffset(struct idescriptor *d, __address offset)
		86	{
		87	d->offset_0_15 = offset & 0xffff;
		88	d->offset_16_31 = offset >> 16;
		89	}
		90
		91	void tss_initialize(struct tss *t)
		92	{
		93	memsetb((__address) t, sizeof(struct tss), 0);
		94	}
		95
		96	/*
		97	* This function takes care of proper setup of IDT and IDTR.
		98	*/
		99	void idt_init(void)
		100	{
		101	struct idescriptor *d;
		102	int i;
		103
		104	for (i = 0; i < IDT_ITEMS; i++) {
		105	d = &idt[i];
		106
		107	d->unused = 0;
		108	d->selector = selector(KTEXT_DES);
		109
		110	d->access = AR_PRESENT \| AR_INTERRUPT; /* masking interrupt */
		111
		112	if (i == VECTOR_SYSCALL) {
		113	/*
		114	* The syscall interrupt gate must be calleable from userland.
		115	*/
		116	d->access \|= DPL_USER;
		117	}
		118
		119	idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
		120	trap_register(i, null_interrupt);
		121	}
		122	trap_register(13, gp_fault);
		123	}
		124
		125
		126	void pm_init(void)
		127	{
		128	struct descriptor gdt_p = (struct descriptor ) gdtr.base;
		129
		130	/*
		131	* Each CPU has its private GDT and TSS.
		132	* All CPUs share one IDT.
		133	*/
		134
		135	if (config.cpu_active == 1) {
		136	idt_init();
		137	/*
		138	* NOTE: bootstrap CPU has statically allocated TSS, because
		139	* the heap hasn't been initialized so far.
		140	*/
		141	tss_p = &tss;
		142	}
		143	else {
		144	tss_p = (struct tss *) malloc(sizeof(struct tss));
		145	if (!tss_p)
		146	panic(PANIC "could not allocate TSS\n");
		147	}
		148
		149	tss_initialize(tss_p);
		150
		151	gdt_p[TSS_DES].access = AR_PRESENT \| AR_TSS \| DPL_KERNEL;
		152	gdt_p[TSS_DES].special = 1;
		153	gdt_p[TSS_DES].granularity = 1;
		154
		155	gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
		156	gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
		157
		158	/*
		159	* As of this moment, the current CPU has its own GDT pointing
		160	* to its own TSS. We just need to load the TR register.
		161	*/
		162	__asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
		163	}

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(root)/trunk/kernel/arch/ia32/src/pm.c @ 3458 – Rev 16