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1 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2001-2004 Jakub Jermar
1 jermar 3
 * All rights reserved.
4
 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
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1888 jermar 29
/** @addtogroup ia32   
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
1888 jermar 35
#ifndef KERN_ia32_APIC_H_
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#define KERN_ia32_APIC_H_
1 jermar 37
 
38
#include <arch/types.h>
39
#include <cpu.h>
40
 
41
#define FIXED       (0<<0)
42
#define LOPRI       (1<<0)
43
 
515 jermar 44
#define APIC_ID_COUNT   16
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1 jermar 46
/* local APIC macros */
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#define IPI_INIT    0
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#define IPI_STARTUP 0
49
 
513 jermar 50
/** Delivery modes. */
51
#define DELMOD_FIXED    0x0
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#define DELMOD_LOWPRI   0x1
53
#define DELMOD_SMI  0x2
54
/* 0x3 reserved */
55
#define DELMOD_NMI  0x4
56
#define DELMOD_INIT 0x5
57
#define DELMOD_STARTUP  0x6
58
#define DELMOD_EXTINT   0x7
1 jermar 59
 
513 jermar 60
/** Destination modes. */
61
#define DESTMOD_PHYS    0x0
62
#define DESTMOD_LOGIC   0x1
63
 
64
/** Trigger Modes. */
65
#define TRIGMOD_EDGE    0x0
66
#define TRIGMOD_LEVEL   0x1
67
 
68
/** Levels. */
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#define LEVEL_DEASSERT  0x0
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#define LEVEL_ASSERT    0x1
71
 
72
/** Destination Shorthands. */
73
#define SHORTHAND_NONE      0x0
74
#define SHORTHAND_SELF      0x1
75
#define SHORTHAND_ALL_INCL  0x2
76
#define SHORTHAND_ALL_EXCL  0x3
77
 
78
/** Interrupt Input Pin Polarities. */
79
#define POLARITY_HIGH   0x0
80
#define POLARITY_LOW    0x1
81
 
514 jermar 82
/** Divide Values. (Bit 2 is always 0) */
83
#define DIVIDE_2    0x0
84
#define DIVIDE_4    0x1
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#define DIVIDE_8    0x2
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#define DIVIDE_16   0x3
87
#define DIVIDE_32   0x8
88
#define DIVIDE_64   0x9
89
#define DIVIDE_128  0xa
90
#define DIVIDE_1    0xb
91
 
92
/** Timer Modes. */
93
#define TIMER_ONESHOT   0x0
94
#define TIMER_PERIODIC  0x1
95
 
515 jermar 96
/** Delivery status. */
97
#define DELIVS_IDLE 0x0
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#define DELIVS_PENDING  0x1
1 jermar 99
 
515 jermar 100
/** Destination masks. */
101
#define DEST_ALL    0xff
102
 
672 jermar 103
/** Dest format models. */
104
#define MODEL_FLAT  0xf
105
#define MODEL_CLUSTER   0x0
106
 
513 jermar 107
/** Interrupt Command Register. */
1780 jermar 108
#define ICRlo       (0x300/sizeof(uint32_t))
109
#define ICRhi       (0x310/sizeof(uint32_t))
513 jermar 110
struct icr {
111
    union {
1780 jermar 112
        uint32_t lo;
513 jermar 113
        struct {
1780 jermar 114
            uint8_t vector;         /**< Interrupt Vector. */
513 jermar 115
            unsigned delmod : 3;        /**< Delivery Mode. */
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            unsigned destmod : 1;       /**< Destination Mode. */
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            unsigned delivs : 1;        /**< Delivery status (RO). */
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            unsigned : 1;           /**< Reserved. */
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            unsigned level : 1;     /**< Level. */
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            unsigned trigger_mode : 1;  /**< Trigger Mode. */
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            unsigned : 2;           /**< Reserved. */
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            unsigned shorthand : 2;     /**< Destination Shorthand. */
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            unsigned : 12;          /**< Reserved. */
124
        } __attribute__ ((packed));
125
    };
126
    union {
1780 jermar 127
        uint32_t hi;
513 jermar 128
        struct {
129
            unsigned : 24;          /**< Reserved. */
1780 jermar 130
            uint8_t dest;           /**< Destination field. */
513 jermar 131
        } __attribute__ ((packed));
132
    };
133
} __attribute__ ((packed));
134
typedef struct icr icr_t;
1 jermar 135
 
1251 jermar 136
/* End Of Interrupt. */
1780 jermar 137
#define EOI     (0x0b0/sizeof(uint32_t))
1 jermar 138
 
514 jermar 139
/** Error Status Register. */
1780 jermar 140
#define ESR     (0x280/sizeof(uint32_t))
514 jermar 141
union esr {
1780 jermar 142
    uint32_t value;
143
    uint8_t err_bitmap;
514 jermar 144
    struct {
145
        unsigned send_checksum_error : 1;
146
        unsigned receive_checksum_error : 1;
147
        unsigned send_accept_error : 1;
148
        unsigned receive_accept_error : 1;
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        unsigned : 1;
150
        unsigned send_illegal_vector : 1;
151
        unsigned received_illegal_vector : 1;
152
        unsigned illegal_register_address : 1;
153
        unsigned : 24;
154
    } __attribute__ ((packed));
155
};
156
typedef union esr esr_t;
1 jermar 157
 
158
/* Task Priority Register */
1780 jermar 159
#define TPR     (0x080/sizeof(uint32_t))
750 jermar 160
union tpr {
1780 jermar 161
    uint32_t value;
750 jermar 162
    struct {
163
        unsigned pri_sc : 4;        /**< Task Priority Sub-Class. */
164
        unsigned pri : 4;       /**< Task Priority. */
165
    } __attribute__ ((packed));
166
};
167
typedef union tpr tpr_t;
1 jermar 168
 
513 jermar 169
/** Spurious-Interrupt Vector Register. */
1780 jermar 170
#define SVR     (0x0f0/sizeof(uint32_t))
513 jermar 171
union svr {
1780 jermar 172
    uint32_t value;
513 jermar 173
    struct {
1780 jermar 174
        uint8_t vector;         /**< Spurious Vector. */
750 jermar 175
        unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */
176
        unsigned focus_checking : 1;    /**< Focus Processor Checking. */
513 jermar 177
        unsigned : 22;          /**< Reserved. */
178
    } __attribute__ ((packed));
179
};
180
typedef union svr svr_t;
1 jermar 181
 
514 jermar 182
/** Time Divide Configuration Register. */
1780 jermar 183
#define TDCR        (0x3e0/sizeof(uint32_t))
514 jermar 184
union tdcr {
1780 jermar 185
    uint32_t value;
514 jermar 186
    struct {
187
        unsigned div_value : 4;     /**< Divide Value, bit 2 is always 0. */
188
        unsigned : 28;          /**< Reserved. */
189
    } __attribute__ ((packed));
190
};
191
typedef union tdcr tdcr_t;
1 jermar 192
 
193
/* Initial Count Register for Timer */
1780 jermar 194
#define ICRT        (0x380/sizeof(uint32_t))
1 jermar 195
 
196
/* Current Count Register for Timer */
1780 jermar 197
#define CCRT        (0x390/sizeof(uint32_t))
1 jermar 198
 
513 jermar 199
/** LVT Timer register. */
1780 jermar 200
#define LVT_Tm      (0x320/sizeof(uint32_t))
513 jermar 201
union lvt_tm {
1780 jermar 202
    uint32_t value;
513 jermar 203
    struct {
1780 jermar 204
        uint8_t vector;     /**< Local Timer Interrupt vector. */
513 jermar 205
        unsigned : 4;       /**< Reserved. */
206
        unsigned delivs : 1;    /**< Delivery status (RO). */
207
        unsigned : 3;       /**< Reserved. */
208
        unsigned masked : 1;    /**< Interrupt Mask. */
209
        unsigned mode : 1;  /**< Timer Mode. */
210
        unsigned : 14;      /**< Reserved. */
211
    } __attribute__ ((packed));
212
};
213
typedef union lvt_tm lvt_tm_t;
214
 
215
/** LVT LINT registers. */
1780 jermar 216
#define LVT_LINT0   (0x350/sizeof(uint32_t))
217
#define LVT_LINT1   (0x360/sizeof(uint32_t))
513 jermar 218
union lvt_lint {
1780 jermar 219
    uint32_t value;
513 jermar 220
    struct {
1780 jermar 221
        uint8_t vector;         /**< LINT Interrupt vector. */
513 jermar 222
        unsigned delmod : 3;        /**< Delivery Mode. */
223
        unsigned : 1;           /**< Reserved. */
224
        unsigned delivs : 1;        /**< Delivery status (RO). */
225
        unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
226
        unsigned irr : 1;       /**< Remote IRR (RO). */
227
        unsigned trigger_mode : 1;  /**< Trigger Mode. */
228
        unsigned masked : 1;        /**< Interrupt Mask. */
229
        unsigned : 15;          /**< Reserved. */
230
    } __attribute__ ((packed));
231
};
232
typedef union lvt_lint lvt_lint_t;
233
 
234
/** LVT Error register. */
1780 jermar 235
#define LVT_Err     (0x370/sizeof(uint32_t))
513 jermar 236
union lvt_error {
1780 jermar 237
    uint32_t value;
513 jermar 238
    struct {
1780 jermar 239
        uint8_t vector;     /**< Local Timer Interrupt vector. */
513 jermar 240
        unsigned : 4;       /**< Reserved. */
241
        unsigned delivs : 1;    /**< Delivery status (RO). */
242
        unsigned : 3;       /**< Reserved. */
243
        unsigned masked : 1;    /**< Interrupt Mask. */
244
        unsigned : 15;      /**< Reserved. */
245
    } __attribute__ ((packed));
246
};
247
typedef union lvt_error lvt_error_t;
248
 
514 jermar 249
/** Local APIC ID Register. */
1780 jermar 250
#define L_APIC_ID   (0x020/sizeof(uint32_t))
515 jermar 251
union l_apic_id {
1780 jermar 252
    uint32_t value;
514 jermar 253
    struct {
254
        unsigned : 24;      /**< Reserved. */
1780 jermar 255
        uint8_t apic_id;        /**< Local APIC ID. */
514 jermar 256
    } __attribute__ ((packed));
257
};
515 jermar 258
typedef union l_apic_id l_apic_id_t;
1 jermar 259
 
1251 jermar 260
/** Local APIC Version Register */
1780 jermar 261
#define LAVR        (0x030/sizeof(uint32_t))
27 jermar 262
#define LAVR_Mask   0xff
263
#define is_local_apic(x)    (((x)&LAVR_Mask&0xf0)==0x1)
264
#define is_82489DX_apic(x)  ((((x)&LAVR_Mask&0xf0)==0x0))
265
#define is_local_xapic(x)   (((x)&LAVR_Mask)==0x14)
266
 
672 jermar 267
/** Logical Destination Register. */
1780 jermar 268
#define  LDR        (0x0d0/sizeof(uint32_t))
672 jermar 269
union ldr {
1780 jermar 270
    uint32_t value;
672 jermar 271
    struct {
1251 jermar 272
        unsigned : 24;      /**< Reserved. */
1780 jermar 273
        uint8_t id;     /**< Logical APIC ID. */
672 jermar 274
    } __attribute__ ((packed));
275
};
276
typedef union ldr ldr_t;
277
 
278
/** Destination Format Register. */
1780 jermar 279
#define DFR     (0x0e0/sizeof(uint32_t))
672 jermar 280
union dfr {
1780 jermar 281
    uint32_t value;
672 jermar 282
    struct {
283
        unsigned : 28;      /**< Reserved, all ones. */
284
        unsigned model : 4; /**< Model. */
285
    } __attribute__ ((packed));
286
};
287
typedef union dfr dfr_t;
288
 
1 jermar 289
/* IO APIC */
1780 jermar 290
#define IOREGSEL    (0x00/sizeof(uint32_t))
291
#define IOWIN       (0x10/sizeof(uint32_t))
1 jermar 292
 
293
#define IOAPICID    0x00
294
#define IOAPICVER   0x01
295
#define IOAPICARB   0x02
296
#define IOREDTBL    0x10
297
 
514 jermar 298
/** I/O Register Select Register. */
299
union io_regsel {
1780 jermar 300
    uint32_t value;
514 jermar 301
    struct {
1780 jermar 302
        uint8_t reg_addr;       /**< APIC Register Address. */
514 jermar 303
        unsigned : 24;      /**< Reserved. */
304
    } __attribute__ ((packed));
305
};
306
typedef union io_regsel io_regsel_t;
307
 
512 jermar 308
/** I/O Redirection Register. */
309
struct io_redirection_reg {
310
    union {
1780 jermar 311
        uint32_t lo;
512 jermar 312
        struct {
1780 jermar 313
            uint8_t intvec;         /**< Interrupt Vector. */
512 jermar 314
            unsigned delmod : 3;        /**< Delivery Mode. */
315
            unsigned destmod : 1;       /**< Destination mode. */
316
            unsigned delivs : 1;        /**< Delivery status (RO). */
317
            unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
318
            unsigned irr : 1;       /**< Remote IRR (RO). */
319
            unsigned trigger_mode : 1;  /**< Trigger Mode. */
320
            unsigned masked : 1;        /**< Interrupt Mask. */
321
            unsigned : 15;          /**< Reserved. */
513 jermar 322
        } __attribute__ ((packed));
512 jermar 323
    };
324
    union {
1780 jermar 325
        uint32_t hi;
512 jermar 326
        struct {
327
            unsigned : 24;          /**< Reserved. */
1780 jermar 328
            uint8_t dest : 8;           /**< Destination Field. */
513 jermar 329
        } __attribute__ ((packed));
512 jermar 330
    };
331
 
332
} __attribute__ ((packed));
333
typedef struct io_redirection_reg io_redirection_reg_t;
334
 
515 jermar 335
 
336
/** IO APIC Identification Register. */
337
union io_apic_id {
1780 jermar 338
    uint32_t value;
515 jermar 339
    struct {
340
        unsigned : 24;      /**< Reserved. */
341
        unsigned apic_id : 4;   /**< IO APIC ID. */
342
        unsigned : 4;       /**< Reserved. */
343
    } __attribute__ ((packed));
344
};
345
typedef union io_apic_id io_apic_id_t;
346
 
1780 jermar 347
extern volatile uint32_t *l_apic;
348
extern volatile uint32_t *io_apic;
1 jermar 349
 
1780 jermar 350
extern uint32_t apic_id_mask;
1 jermar 351
 
352
extern void apic_init(void);
353
 
354
extern void l_apic_init(void);
355
extern void l_apic_eoi(void);
1780 jermar 356
extern int l_apic_broadcast_custom_ipi(uint8_t vector);
357
extern int l_apic_send_init_ipi(uint8_t apicid);
1 jermar 358
extern void l_apic_debug(void);
1780 jermar 359
extern uint8_t l_apic_id(void);
1 jermar 360
 
1780 jermar 361
extern uint32_t io_apic_read(uint8_t address);
362
extern void io_apic_write(uint8_t address , uint32_t x);
363
extern void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags);
364
extern void io_apic_disable_irqs(uint16_t irqmask);
365
extern void io_apic_enable_irqs(uint16_t irqmask);
1 jermar 366
 
367
#endif
1702 cejka 368
 
1888 jermar 369
/** @}
1702 cejka 370
 */