Subversion Repositories HelenOS

Rev

Rev 3902 | Rev 3946 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
1 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2001-2004 Jakub Jermar
3
 * Copyright (c) 2005 Sergey Bondari
1 jermar 4
 * All rights reserved.
5
 *
6
 * Redistribution and use in source and binary forms, with or without
7
 * modification, are permitted provided that the following conditions
8
 * are met:
9
 *
10
 * - Redistributions of source code must retain the above copyright
11
 *   notice, this list of conditions and the following disclaimer.
12
 * - Redistributions in binary form must reproduce the above copyright
13
 *   notice, this list of conditions and the following disclaimer in the
14
 *   documentation and/or other materials provided with the distribution.
15
 * - The name of the author may not be used to endorse or promote products
16
 *   derived from this software without specific prior written permission.
17
 *
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
 */
29
 
1888 jermar 30
/** @addtogroup ia32   
1702 cejka 31
 * @{
32
 */
33
/** @file
34
 */
35
 
1888 jermar 36
#ifndef KERN_ia32_ASM_H_
37
#define KERN_ia32_ASM_H_
1 jermar 38
 
1186 jermar 39
#include <arch/pm.h>
1 jermar 40
#include <arch/types.h>
177 jermar 41
#include <config.h>
1 jermar 42
 
1780 jermar 43
extern uint32_t interrupt_handler_size;
1 jermar 44
 
45
extern void paging_on(void);
46
 
47
extern void interrupt_handlers(void);
48
 
49
extern void enable_l_apic_in_msr(void);
50
 
195 vana 51
 
1780 jermar 52
extern void asm_delay_loop(uint32_t t);
53
extern void asm_fake_loop(uint32_t t);
195 vana 54
 
55
 
115 jermar 56
/** Halt CPU
57
 *
58
 * Halt the current CPU until interrupt event.
59
 */
2082 decky 60
static inline void cpu_halt(void)
61
{
2233 decky 62
    asm volatile ("hlt\n");
2444 jermar 63
}
1 jermar 64
 
2082 decky 65
static inline void cpu_sleep(void)
66
{
2233 decky 67
    asm volatile ("hlt\n");
2444 jermar 68
}
2082 decky 69
 
1780 jermar 70
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
1074 palkovsky 71
    { \
1780 jermar 72
    unative_t res; \
2082 decky 73
    asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
1074 palkovsky 74
    return res; \
75
    }
27 jermar 76
 
1780 jermar 77
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
1074 palkovsky 78
    { \
2082 decky 79
    asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
1074 palkovsky 80
    }
38 jermar 81
 
2444 jermar 82
GEN_READ_REG(cr0)
83
GEN_READ_REG(cr2)
84
GEN_READ_REG(cr3)
85
GEN_WRITE_REG(cr3)
115 jermar 86
 
2444 jermar 87
GEN_READ_REG(dr0)
88
GEN_READ_REG(dr1)
89
GEN_READ_REG(dr2)
90
GEN_READ_REG(dr3)
91
GEN_READ_REG(dr6)
92
GEN_READ_REG(dr7)
1074 palkovsky 93
 
2444 jermar 94
GEN_WRITE_REG(dr0)
95
GEN_WRITE_REG(dr1)
96
GEN_WRITE_REG(dr2)
97
GEN_WRITE_REG(dr3)
98
GEN_WRITE_REG(dr6)
99
GEN_WRITE_REG(dr7)
1074 palkovsky 100
 
352 bondari 101
/** Byte to port
102
 *
103
 * Output byte to port
104
 *
105
 * @param port Port to write to
106
 * @param val Value to write
107
 */
3929 jermar 108
static inline void pio_write_8(ioport8_t *port, uint8_t val)
2082 decky 109
{
3929 jermar 110
    asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port));
2082 decky 111
}
352 bondari 112
 
353 bondari 113
/** Word to port
114
 *
115
 * Output word to port
116
 *
117
 * @param port Port to write to
118
 * @param val Value to write
119
 */
3929 jermar 120
static inline void pio_write_16(ioport16_t *port, uint16_t val)
2082 decky 121
{
3929 jermar 122
    asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port));
2082 decky 123
}
352 bondari 124
 
353 bondari 125
/** Double word to port
126
 *
127
 * Output double word to port
128
 *
129
 * @param port Port to write to
130
 * @param val Value to write
131
 */
3929 jermar 132
static inline void pio_write_32(ioport32_t *port, uint32_t val)
2082 decky 133
{
3929 jermar 134
    asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port));
2082 decky 135
}
353 bondari 136
 
356 bondari 137
/** Byte from port
138
 *
139
 * Get byte from port
140
 *
141
 * @param port Port to read from
142
 * @return Value read
143
 */
3929 jermar 144
static inline uint8_t pio_read_8(ioport8_t *port)
2082 decky 145
{
146
    uint8_t val;
147
 
3929 jermar 148
    asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port));
2082 decky 149
    return val;
150
}
356 bondari 151
 
152
/** Word from port
153
 *
154
 * Get word from port
155
 *
156
 * @param port Port to read from
157
 * @return Value read
158
 */
3929 jermar 159
static inline uint16_t pio_read_16(ioport16_t *port)
2082 decky 160
{
161
    uint16_t val;
162
 
3929 jermar 163
    asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port));
2082 decky 164
    return val;
165
}
356 bondari 166
 
167
/** Double word from port
168
 *
169
 * Get double word from port
170
 *
171
 * @param port Port to read from
172
 * @return Value read
173
 */
3929 jermar 174
static inline uint32_t pio_read_32(ioport32_t *port)
2082 decky 175
{
176
    uint32_t val;
177
 
3929 jermar 178
    asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port));
2082 decky 179
    return val;
180
}
356 bondari 181
 
413 jermar 182
/** Enable interrupts.
115 jermar 183
 *
184
 * Enable interrupts and return previous
185
 * value of EFLAGS.
413 jermar 186
 *
187
 * @return Old interrupt priority level.
115 jermar 188
 */
432 jermar 189
static inline ipl_t interrupts_enable(void)
190
{
413 jermar 191
    ipl_t v;
2082 decky 192
    asm volatile (
358 bondari 193
        "pushf\n\t"
194
        "popl %0\n\t"
115 jermar 195
        "sti\n"
196
        : "=r" (v)
197
    );
198
    return v;
199
}
200
 
413 jermar 201
/** Disable interrupts.
115 jermar 202
 *
203
 * Disable interrupts and return previous
204
 * value of EFLAGS.
413 jermar 205
 *
206
 * @return Old interrupt priority level.
115 jermar 207
 */
432 jermar 208
static inline ipl_t interrupts_disable(void)
209
{
413 jermar 210
    ipl_t v;
2082 decky 211
    asm volatile (
358 bondari 212
        "pushf\n\t"
213
        "popl %0\n\t"
115 jermar 214
        "cli\n"
215
        : "=r" (v)
216
    );
217
    return v;
218
}
219
 
413 jermar 220
/** Restore interrupt priority level.
115 jermar 221
 *
222
 * Restore EFLAGS.
413 jermar 223
 *
224
 * @param ipl Saved interrupt priority level.
115 jermar 225
 */
432 jermar 226
static inline void interrupts_restore(ipl_t ipl)
227
{
2082 decky 228
    asm volatile (
358 bondari 229
        "pushl %0\n\t"
115 jermar 230
        "popf\n"
413 jermar 231
        : : "r" (ipl)
115 jermar 232
    );
233
}
234
 
413 jermar 235
/** Return interrupt priority level.
115 jermar 236
 *
413 jermar 237
 * @return EFLAFS.
115 jermar 238
 */
432 jermar 239
static inline ipl_t interrupts_read(void)
240
{
413 jermar 241
    ipl_t v;
2082 decky 242
    asm volatile (
358 bondari 243
        "pushf\n\t"
115 jermar 244
        "popl %0\n"
245
        : "=r" (v)
246
    );
247
    return v;
248
}
249
 
3485 jermar 250
/** Write to MSR */
251
static inline void write_msr(uint32_t msr, uint64_t value)
252
{
253
    asm volatile ("wrmsr" : : "c" (msr), "a" ((uint32_t)(value)),
254
        "d" ((uint32_t)(value >> 32)));
255
}
256
 
257
static inline uint64_t read_msr(uint32_t msr)
258
{
259
    uint32_t ax, dx;
260
 
261
    asm volatile ("rdmsr" : "=a"(ax), "=d"(dx) : "c" (msr));
262
    return ((uint64_t)dx << 32) | ax;
263
}
264
 
265
 
173 jermar 266
/** Return base address of current stack
267
 *
268
 * Return the base address of the current stack.
269
 * The stack is assumed to be STACK_SIZE bytes long.
180 jermar 270
 * The stack must start on page boundary.
173 jermar 271
 */
1780 jermar 272
static inline uintptr_t get_stack_base(void)
173 jermar 273
{
1780 jermar 274
    uintptr_t v;
173 jermar 275
 
2441 decky 276
    asm volatile (
277
        "andl %%esp, %0\n"
278
        : "=r" (v)
279
        : "0" (~(STACK_SIZE - 1))
280
    );
173 jermar 281
 
282
    return v;
283
}
284
 
581 palkovsky 285
/** Return current IP address */
1780 jermar 286
static inline uintptr_t * get_ip()
581 palkovsky 287
{
1780 jermar 288
    uintptr_t *ip;
581 palkovsky 289
 
2082 decky 290
    asm volatile (
581 palkovsky 291
        "mov %%eip, %0"
292
        : "=r" (ip)
293
        );
294
    return ip;
295
}
296
 
597 jermar 297
/** Invalidate TLB Entry.
298
 *
299
 * @param addr Address on a page whose TLB entry is to be invalidated.
300
 */
1780 jermar 301
static inline void invlpg(uintptr_t addr)
597 jermar 302
{
2082 decky 303
    asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
597 jermar 304
}
305
 
1186 jermar 306
/** Load GDTR register from memory.
307
 *
308
 * @param gdtr_reg Address of memory from where to load GDTR.
309
 */
1187 jermar 310
static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
1186 jermar 311
{
2082 decky 312
    asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
1186 jermar 313
}
314
 
315
/** Store GDTR register to memory.
316
 *
317
 * @param gdtr_reg Address of memory to where to load GDTR.
318
 */
1187 jermar 319
static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
1186 jermar 320
{
2082 decky 321
    asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
1186 jermar 322
}
323
 
324
/** Load IDTR register from memory.
325
 *
326
 * @param idtr_reg Address of memory from where to load IDTR.
327
 */
1187 jermar 328
static inline void idtr_load(ptr_16_32_t *idtr_reg)
1186 jermar 329
{
2082 decky 330
    asm volatile ("lidtl %0\n" : : "m" (*idtr_reg));
1186 jermar 331
}
332
 
333
/** Load TR from descriptor table.
334
 *
335
 * @param sel Selector specifying descriptor of TSS segment.
336
 */
1780 jermar 337
static inline void tr_load(uint16_t sel)
1186 jermar 338
{
2082 decky 339
    asm volatile ("ltr %0" : : "r" (sel));
1186 jermar 340
}
341
 
1 jermar 342
#endif
1702 cejka 343
 
1888 jermar 344
/** @}
1702 cejka 345
 */