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178 palkovsky 1
/*
2071 jermar 2
 * Copyright (c) 2001-2004 Jakub Jermar
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 * Copyright (c) 2005-2006 Ondrej Palkovsky
178 palkovsky 4
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1888 jermar 30
/** @addtogroup amd64  
1702 cejka 31
 * @{
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 */
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/** @file
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 */
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178 palkovsky 36
#include <arch/pm.h>
206 palkovsky 37
#include <arch/asm.h>
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#include <mm/as.h>
2089 decky 39
#include <mm/frame.h>
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#include <memstr.h>
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#include <mm/slab.h>
206 palkovsky 42
 
178 palkovsky 43
/*
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 * There is no segmentation in long mode so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 */
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1187 jermar 49
descriptor_t gdt[GDT_ITEMS] = {
178 palkovsky 50
    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 1,
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      .special     = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* KDATA descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
803 palkovsky 74
    /* UDATA descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 1,
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      .granularity = 1,
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      .base_24_31  = 0 },
803 palkovsky 85
    /* UTEXT descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_USER,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 1,
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      .special     = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* KTEXT 32-bit protected, for protected mode before long mode */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 1,
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      .granularity = 1,
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      .base_24_31  = 0 },
206 palkovsky 107
    /* TSS descriptor - set up will be completed later,
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     * on AMD64 it is 64-bit - 2 items in table */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1289 vana 110
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* VESA Init descriptor */
1292 vana 112
#ifdef CONFIG_FB    
1289 vana 113
    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
1292 vana 114
#endif
178 palkovsky 115
};
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1187 jermar 117
idescriptor_t idt[IDT_ITEMS];
178 palkovsky 118
 
1780 jermar 119
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (uint64_t) gdt };
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ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (uint64_t) idt };
229 palkovsky 121
 
1187 jermar 122
static tss_t tss;
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tss_t *tss_p = NULL;
178 palkovsky 124
 
1780 jermar 125
void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
206 palkovsky 126
{
1187 jermar 127
    tss_descriptor_t *td = (tss_descriptor_t *) d;
206 palkovsky 128
 
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    td->base_0_15 = base & 0xffff;
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    td->base_16_23 = ((base) >> 16) & 0xff;
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    td->base_24_31 = ((base) >> 24) & 0xff;
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    td->base_32_63 = ((base) >> 32);
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}
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1780 jermar 135
void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
206 palkovsky 136
{
1187 jermar 137
    struct tss_descriptor *td = (tss_descriptor_t *) d;
206 palkovsky 138
 
139
    td->limit_0_15 = limit & 0xffff;
140
    td->limit_16_19 = (limit >> 16) & 0xf;
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}
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1780 jermar 143
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
206 palkovsky 144
{
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    /*
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     * Offset is a linear address.
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     */
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    d->offset_0_15 = offset & 0xffff;
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    d->offset_16_31 = offset >> 16 & 0xffff;
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    d->offset_32_63 = offset >> 32;
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}
152
 
1187 jermar 153
void tss_initialize(tss_t *t)
206 palkovsky 154
{
1780 jermar 155
    memsetb((uintptr_t) t, sizeof(tss_t), 0);
206 palkovsky 156
}
157
 
158
/*
159
 * This function takes care of proper setup of IDT and IDTR.
160
 */
161
void idt_init(void)
162
{
1187 jermar 163
    idescriptor_t *d;
206 palkovsky 164
    int i;
165
 
166
    for (i = 0; i < IDT_ITEMS; i++) {
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        d = &idt[i];
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169
        d->unused = 0;
211 palkovsky 170
        d->selector = gdtselector(KTEXT_DES);
206 palkovsky 171
 
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        d->present = 1;
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        d->type = AR_INTERRUPT; /* masking interrupt */
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1780 jermar 175
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i*interrupt_handler_size);
206 palkovsky 176
    }
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}
178
 
799 palkovsky 179
/** Initialize segmentation - code/data/idt tables
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 *
181
 */
206 palkovsky 182
void pm_init(void)
183
{
1187 jermar 184
    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
185
    tss_descriptor_t *tss_desc;
206 palkovsky 186
 
187
    /*
188
     * Each CPU has its private GDT and TSS.
189
     * All CPUs share one IDT.
190
     */
191
 
192
    if (config.cpu_active == 1) {
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        idt_init();
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        /*
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         * NOTE: bootstrap CPU has statically allocated TSS, because
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         * the heap hasn't been initialized so far.
197
         */
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        tss_p = &tss;
199
    }
200
    else {
1252 palkovsky 201
        /* We are going to use malloc, which may return
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         * non boot-mapped pointer, initialize the CR3 register
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         * ahead of page_init */
2106 jermar 204
        write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
1252 palkovsky 205
 
1187 jermar 206
        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
206 palkovsky 207
        if (!tss_p)
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            panic("could not allocate TSS\n");
209
    }
210
 
211
    tss_initialize(tss_p);
212
 
1187 jermar 213
    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
208 palkovsky 214
    tss_desc->present = 1;
215
    tss_desc->type = AR_TSS;
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    tss_desc->dpl = PL_KERNEL;
206 palkovsky 217
 
1780 jermar 218
    gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
1251 jermar 219
    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
206 palkovsky 220
 
1186 jermar 221
    gdtr_load(&gdtr);
222
    idtr_load(&idtr);
206 palkovsky 223
    /*
224
     * As of this moment, the current CPU has its own GDT pointing
225
     * to its own TSS. We just need to load the TR register.
226
     */
1186 jermar 227
    tr_load(gdtselector(TSS_DES));
206 palkovsky 228
}
1702 cejka 229
 
1888 jermar 230
/** @}
1702 cejka 231
 */