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173 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
173 jermar 3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
4017 decky 29
/** @addtogroup amd64
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
1888 jermar 35
#ifndef KERN_amd64_ASM_H_
36
#define KERN_amd64_ASM_H_
173 jermar 37
 
38
#include <config.h>
4021 jermar 39
#include <arch/types.h>
40
#include <typedefs.h>
173 jermar 41
 
1780 jermar 42
extern void asm_delay_loop(uint32_t t);
43
extern void asm_fake_loop(uint32_t t);
200 palkovsky 44
 
253 jermar 45
/** Return base address of current stack.
46
 *
47
 * Return the base address of the current stack.
48
 * The stack is assumed to be STACK_SIZE bytes long.
49
 * The stack must start on page boundary.
4017 decky 50
 *
253 jermar 51
 */
1780 jermar 52
static inline uintptr_t get_stack_base(void)
173 jermar 53
{
1780 jermar 54
    uintptr_t v;
226 palkovsky 55
 
4017 decky 56
    asm volatile (
57
        "andq %%rsp, %[v]\n"
58
        : [v] "=r" (v)
59
        : "0" (~((uint64_t) STACK_SIZE-1))
60
    );
226 palkovsky 61
 
62
    return v;
173 jermar 63
}
64
 
2233 decky 65
static inline void cpu_sleep(void)
66
{
67
    asm volatile ("hlt\n");
2453 jermar 68
}
197 palkovsky 69
 
2233 decky 70
static inline void cpu_halt(void)
71
{
72
    asm volatile ("hlt\n");
2453 jermar 73
}
200 palkovsky 74
 
2233 decky 75
 
625 palkovsky 76
/** Byte from port
77
 *
78
 * Get byte from port
79
 *
80
 * @param port Port to read from
81
 * @return Value read
4017 decky 82
 *
625 palkovsky 83
 */
3929 jermar 84
static inline uint8_t pio_read_8(ioport8_t *port)
2453 jermar 85
{
86
    uint8_t val;
4017 decky 87
 
88
    asm volatile (
89
        "inb %w[port], %b[val]\n"
90
        : [val] "=a" (val)
91
        : [port] "d" (port)
92
    );
93
 
2453 jermar 94
    return val;
95
}
96
 
3948 jermar 97
/** Word from port
98
 *
99
 * Get word from port
100
 *
101
 * @param port Port to read from
102
 * @return Value read
4017 decky 103
 *
3948 jermar 104
 */
105
static inline uint16_t pio_read_16(ioport16_t *port)
106
{
107
    uint16_t val;
108
 
4017 decky 109
    asm volatile (
110
        "inw %w[port], %w[val]\n"
111
        : [val] "=a" (val)
112
        : [port] "d" (port)
113
    );
114
 
3948 jermar 115
    return val;
116
}
117
 
118
/** Double word from port
119
 *
120
 * Get double word from port
121
 *
122
 * @param port Port to read from
123
 * @return Value read
4017 decky 124
 *
3948 jermar 125
 */
126
static inline uint32_t pio_read_32(ioport32_t *port)
127
{
128
    uint32_t val;
129
 
4017 decky 130
    asm volatile (
131
        "inl %w[port], %[val]\n"
132
        : [val] "=a" (val)
133
        : [port] "d" (port)
134
    );
135
 
3948 jermar 136
    return val;
137
}
138
 
625 palkovsky 139
/** Byte to port
140
 *
141
 * Output byte to port
142
 *
143
 * @param port Port to write to
144
 * @param val Value to write
4017 decky 145
 *
625 palkovsky 146
 */
3929 jermar 147
static inline void pio_write_8(ioport8_t *port, uint8_t val)
2453 jermar 148
{
4017 decky 149
    asm volatile (
150
        "outb %b[val], %w[port]\n"
151
        :: [val] "a" (val), [port] "d" (port)
152
    );
2453 jermar 153
}
200 palkovsky 154
 
3948 jermar 155
/** Word to port
156
 *
157
 * Output word to port
158
 *
159
 * @param port Port to write to
160
 * @param val Value to write
4017 decky 161
 *
3948 jermar 162
 */
163
static inline void pio_write_16(ioport16_t *port, uint16_t val)
164
{
4017 decky 165
    asm volatile (
166
        "outw %w[val], %w[port]\n"
167
        :: [val] "a" (val), [port] "d" (port)
168
    );
3948 jermar 169
}
170
 
171
/** Double word to port
172
 *
173
 * Output double word to port
174
 *
175
 * @param port Port to write to
176
 * @param val Value to write
4017 decky 177
 *
3948 jermar 178
 */
179
static inline void pio_write_32(ioport32_t *port, uint32_t val)
180
{
4017 decky 181
    asm volatile (
182
        "outl %[val], %w[port]\n"
183
        :: [val] "a" (val), [port] "d" (port)
184
    );
3948 jermar 185
}
186
 
806 palkovsky 187
/** Swap Hidden part of GS register with visible one */
2453 jermar 188
static inline void swapgs(void)
189
{
190
    asm volatile("swapgs");
191
}
806 palkovsky 192
 
413 jermar 193
/** Enable interrupts.
200 palkovsky 194
 *
195
 * Enable interrupts and return previous
196
 * value of EFLAGS.
413 jermar 197
 *
198
 * @return Old interrupt priority level.
4017 decky 199
 *
200 palkovsky 200
 */
413 jermar 201
static inline ipl_t interrupts_enable(void) {
202
    ipl_t v;
4017 decky 203
 
204
    asm volatile (
200 palkovsky 205
        "pushfq\n"
4017 decky 206
        "popq %[v]\n"
200 palkovsky 207
        "sti\n"
4017 decky 208
        : [v] "=r" (v)
200 palkovsky 209
    );
4017 decky 210
 
200 palkovsky 211
    return v;
212
}
213
 
413 jermar 214
/** Disable interrupts.
200 palkovsky 215
 *
216
 * Disable interrupts and return previous
217
 * value of EFLAGS.
413 jermar 218
 *
219
 * @return Old interrupt priority level.
4017 decky 220
 *
200 palkovsky 221
 */
413 jermar 222
static inline ipl_t interrupts_disable(void) {
223
    ipl_t v;
4017 decky 224
 
225
    asm volatile (
200 palkovsky 226
        "pushfq\n"
4017 decky 227
        "popq %[v]\n"
200 palkovsky 228
        "cli\n"
4017 decky 229
        : [v] "=r" (v)
230
    );
231
 
200 palkovsky 232
    return v;
233
}
234
 
413 jermar 235
/** Restore interrupt priority level.
200 palkovsky 236
 *
237
 * Restore EFLAGS.
413 jermar 238
 *
239
 * @param ipl Saved interrupt priority level.
4017 decky 240
 *
200 palkovsky 241
 */
413 jermar 242
static inline void interrupts_restore(ipl_t ipl) {
4017 decky 243
    asm volatile (
244
        "pushq %[ipl]\n"
200 palkovsky 245
        "popfq\n"
4017 decky 246
        :: [ipl] "r" (ipl)
247
    );
200 palkovsky 248
}
249
 
413 jermar 250
/** Return interrupt priority level.
206 palkovsky 251
 *
252
 * Return EFLAFS.
413 jermar 253
 *
254
 * @return Current interrupt priority level.
4017 decky 255
 *
206 palkovsky 256
 */
413 jermar 257
static inline ipl_t interrupts_read(void) {
258
    ipl_t v;
4017 decky 259
 
260
    asm volatile (
206 palkovsky 261
        "pushfq\n"
4017 decky 262
        "popq %[v]\n"
263
        : [v] "=r" (v)
206 palkovsky 264
    );
4017 decky 265
 
206 palkovsky 266
    return v;
267
}
200 palkovsky 268
 
803 palkovsky 269
/** Write to MSR */
1780 jermar 270
static inline void write_msr(uint32_t msr, uint64_t value)
803 palkovsky 271
{
4017 decky 272
    asm volatile (
273
        "wrmsr\n"
274
        :: "c" (msr),
275
           "a" ((uint32_t) (value)),
276
           "d" ((uint32_t) (value >> 32))
277
    );
803 palkovsky 278
}
219 palkovsky 279
 
1780 jermar 280
static inline unative_t read_msr(uint32_t msr)
803 palkovsky 281
{
1780 jermar 282
    uint32_t ax, dx;
4017 decky 283
 
284
    asm volatile (
285
        "rdmsr\n"
286
        : "=a" (ax), "=d" (dx)
287
        : "c" (msr)
288
    );
289
 
290
    return ((uint64_t) dx << 32) | ax;
803 palkovsky 291
}
292
 
293
 
268 palkovsky 294
/** Enable local APIC
295
 *
296
 * Enable local APIC in MSR.
4017 decky 297
 *
268 palkovsky 298
 */
299
static inline void enable_l_apic_in_msr()
300
{
4017 decky 301
    asm volatile (
348 jermar 302
        "movl $0x1b, %%ecx\n"
303
        "rdmsr\n"
4017 decky 304
        "orl $(1 << 11),%%eax\n"
348 jermar 305
        "orl $(0xfee00000),%%eax\n"
306
        "wrmsr\n"
4017 decky 307
        ::: "%eax","%ecx","%edx"
308
    );
268 palkovsky 309
}
310
 
1780 jermar 311
static inline uintptr_t * get_ip()
581 palkovsky 312
{
1780 jermar 313
    uintptr_t *ip;
4017 decky 314
 
315
    asm volatile (
316
        "mov %%rip, %[ip]"
317
        : [ip] "=r" (ip)
318
    );
319
 
581 palkovsky 320
    return ip;
321
}
322
 
597 jermar 323
/** Invalidate TLB Entry.
324
 *
325
 * @param addr Address on a page whose TLB entry is to be invalidated.
4017 decky 326
 *
597 jermar 327
 */
1780 jermar 328
static inline void invlpg(uintptr_t addr)
597 jermar 329
{
4017 decky 330
    asm volatile (
331
        "invlpg %[addr]\n"
332
        :: [addr] "m" (*((unative_t *) addr))
333
    );
597 jermar 334
}
581 palkovsky 335
 
1186 jermar 336
/** Load GDTR register from memory.
337
 *
338
 * @param gdtr_reg Address of memory from where to load GDTR.
4017 decky 339
 *
1186 jermar 340
 */
341
static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
342
{
4017 decky 343
    asm volatile (
344
        "lgdtq %[gdtr_reg]\n"
345
        :: [gdtr_reg] "m" (*gdtr_reg)
346
    );
1186 jermar 347
}
348
 
349
/** Store GDTR register to memory.
350
 *
351
 * @param gdtr_reg Address of memory to where to load GDTR.
4017 decky 352
 *
1186 jermar 353
 */
354
static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
355
{
4017 decky 356
    asm volatile (
357
        "sgdtq %[gdtr_reg]\n"
358
        :: [gdtr_reg] "m" (*gdtr_reg)
359
    );
1186 jermar 360
}
361
 
362
/** Load IDTR register from memory.
363
 *
364
 * @param idtr_reg Address of memory from where to load IDTR.
4017 decky 365
 *
1186 jermar 366
 */
367
static inline void idtr_load(struct ptr_16_64 *idtr_reg)
368
{
4017 decky 369
    asm volatile (
370
        "lidtq %[idtr_reg]\n"
371
        :: [idtr_reg] "m" (*idtr_reg));
1186 jermar 372
}
373
 
374
/** Load TR from descriptor table.
375
 *
376
 * @param sel Selector specifying descriptor of TSS segment.
4017 decky 377
 *
1186 jermar 378
 */
1780 jermar 379
static inline void tr_load(uint16_t sel)
1186 jermar 380
{
4017 decky 381
    asm volatile (
382
        "ltr %[sel]"
383
        :: [sel] "r" (sel)
384
    );
1186 jermar 385
}
386
 
1780 jermar 387
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
4017 decky 388
    { \
389
        unative_t res; \
390
        asm volatile ( \
391
            "movq %%" #reg ", %[res]" \
392
            : [res] "=r" (res) \
393
        ); \
394
        return res; \
395
    }
1072 palkovsky 396
 
1780 jermar 397
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
4017 decky 398
    { \
399
        asm volatile ( \
400
            "movq %[regn], %%" #reg \
401
            :: [regn] "r" (regn) \
402
        ); \
403
    }
1072 palkovsky 404
 
2452 jermar 405
GEN_READ_REG(cr0)
406
GEN_READ_REG(cr2)
407
GEN_READ_REG(cr3)
408
GEN_WRITE_REG(cr3)
1072 palkovsky 409
 
2452 jermar 410
GEN_READ_REG(dr0)
411
GEN_READ_REG(dr1)
412
GEN_READ_REG(dr2)
413
GEN_READ_REG(dr3)
414
GEN_READ_REG(dr6)
415
GEN_READ_REG(dr7)
1072 palkovsky 416
 
2452 jermar 417
GEN_WRITE_REG(dr0)
418
GEN_WRITE_REG(dr1)
419
GEN_WRITE_REG(dr2)
420
GEN_WRITE_REG(dr3)
421
GEN_WRITE_REG(dr6)
422
GEN_WRITE_REG(dr7)
1072 palkovsky 423
 
206 palkovsky 424
extern size_t interrupt_handler_size;
425
extern void interrupt_handlers(void);
426
 
173 jermar 427
#endif
1702 cejka 428
 
1888 jermar 429
/** @}
1702 cejka 430
 */