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1 | jermar | 1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #ifndef __APIC_H__ |
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30 | #define __APIC_H__ |
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31 | |||
32 | #include <arch/types.h> |
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33 | #include <cpu.h> |
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34 | |||
35 | #define FIXED (0<<0) |
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36 | #define LOPRI (1<<0) |
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37 | |||
515 | jermar | 38 | #define APIC_ID_COUNT 16 |
39 | |||
1 | jermar | 40 | /* local APIC macros */ |
41 | #define IPI_INIT 0 |
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42 | #define IPI_STARTUP 0 |
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43 | |||
513 | jermar | 44 | /** Delivery modes. */ |
45 | #define DELMOD_FIXED 0x0 |
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46 | #define DELMOD_LOWPRI 0x1 |
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47 | #define DELMOD_SMI 0x2 |
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48 | /* 0x3 reserved */ |
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49 | #define DELMOD_NMI 0x4 |
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50 | #define DELMOD_INIT 0x5 |
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51 | #define DELMOD_STARTUP 0x6 |
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52 | #define DELMOD_EXTINT 0x7 |
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1 | jermar | 53 | |
513 | jermar | 54 | /** Destination modes. */ |
55 | #define DESTMOD_PHYS 0x0 |
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56 | #define DESTMOD_LOGIC 0x1 |
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57 | |||
58 | /** Trigger Modes. */ |
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59 | #define TRIGMOD_EDGE 0x0 |
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60 | #define TRIGMOD_LEVEL 0x1 |
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61 | |||
62 | /** Levels. */ |
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63 | #define LEVEL_DEASSERT 0x0 |
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64 | #define LEVEL_ASSERT 0x1 |
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65 | |||
66 | /** Destination Shorthands. */ |
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67 | #define SHORTHAND_NONE 0x0 |
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68 | #define SHORTHAND_SELF 0x1 |
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69 | #define SHORTHAND_ALL_INCL 0x2 |
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70 | #define SHORTHAND_ALL_EXCL 0x3 |
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71 | |||
72 | /** Interrupt Input Pin Polarities. */ |
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73 | #define POLARITY_HIGH 0x0 |
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74 | #define POLARITY_LOW 0x1 |
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75 | |||
514 | jermar | 76 | /** Divide Values. (Bit 2 is always 0) */ |
77 | #define DIVIDE_2 0x0 |
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78 | #define DIVIDE_4 0x1 |
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79 | #define DIVIDE_8 0x2 |
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80 | #define DIVIDE_16 0x3 |
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81 | #define DIVIDE_32 0x8 |
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82 | #define DIVIDE_64 0x9 |
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83 | #define DIVIDE_128 0xa |
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84 | #define DIVIDE_1 0xb |
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85 | |||
86 | /** Timer Modes. */ |
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87 | #define TIMER_ONESHOT 0x0 |
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88 | #define TIMER_PERIODIC 0x1 |
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89 | |||
515 | jermar | 90 | /** Delivery status. */ |
91 | #define DELIVS_IDLE 0x0 |
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92 | #define DELIVS_PENDING 0x1 |
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1 | jermar | 93 | |
515 | jermar | 94 | /** Destination masks. */ |
95 | #define DEST_ALL 0xff |
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96 | |||
672 | jermar | 97 | /** Dest format models. */ |
98 | #define MODEL_FLAT 0xf |
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99 | #define MODEL_CLUSTER 0x0 |
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100 | |||
513 | jermar | 101 | /** Interrupt Command Register. */ |
1 | jermar | 102 | #define ICRlo (0x300/sizeof(__u32)) |
103 | #define ICRhi (0x310/sizeof(__u32)) |
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513 | jermar | 104 | struct icr { |
105 | union { |
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106 | __u32 lo; |
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107 | struct { |
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108 | __u8 vector; /**< Interrupt Vector. */ |
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109 | unsigned delmod : 3; /**< Delivery Mode. */ |
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110 | unsigned destmod : 1; /**< Destination Mode. */ |
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111 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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112 | unsigned : 1; /**< Reserved. */ |
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113 | unsigned level : 1; /**< Level. */ |
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114 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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115 | unsigned : 2; /**< Reserved. */ |
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116 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
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117 | unsigned : 12; /**< Reserved. */ |
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118 | } __attribute__ ((packed)); |
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119 | }; |
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120 | union { |
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121 | __u32 hi; |
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122 | struct { |
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123 | unsigned : 24; /**< Reserved. */ |
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124 | __u8 dest; /**< Destination field. */ |
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125 | } __attribute__ ((packed)); |
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126 | }; |
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127 | } __attribute__ ((packed)); |
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128 | typedef struct icr icr_t; |
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1 | jermar | 129 | |
1251 | jermar | 130 | /* End Of Interrupt. */ |
1 | jermar | 131 | #define EOI (0x0b0/sizeof(__u32)) |
132 | |||
514 | jermar | 133 | /** Error Status Register. */ |
1 | jermar | 134 | #define ESR (0x280/sizeof(__u32)) |
514 | jermar | 135 | union esr { |
136 | __u32 value; |
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137 | __u8 err_bitmap; |
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138 | struct { |
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139 | unsigned send_checksum_error : 1; |
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140 | unsigned receive_checksum_error : 1; |
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141 | unsigned send_accept_error : 1; |
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142 | unsigned receive_accept_error : 1; |
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143 | unsigned : 1; |
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144 | unsigned send_illegal_vector : 1; |
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145 | unsigned received_illegal_vector : 1; |
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146 | unsigned illegal_register_address : 1; |
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147 | unsigned : 24; |
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148 | } __attribute__ ((packed)); |
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149 | }; |
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150 | typedef union esr esr_t; |
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1 | jermar | 151 | |
152 | /* Task Priority Register */ |
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153 | #define TPR (0x080/sizeof(__u32)) |
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750 | jermar | 154 | union tpr { |
155 | __u32 value; |
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156 | struct { |
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157 | unsigned pri_sc : 4; /**< Task Priority Sub-Class. */ |
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158 | unsigned pri : 4; /**< Task Priority. */ |
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159 | } __attribute__ ((packed)); |
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160 | }; |
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161 | typedef union tpr tpr_t; |
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1 | jermar | 162 | |
513 | jermar | 163 | /** Spurious-Interrupt Vector Register. */ |
1 | jermar | 164 | #define SVR (0x0f0/sizeof(__u32)) |
513 | jermar | 165 | union svr { |
166 | __u32 value; |
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167 | struct { |
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750 | jermar | 168 | __u8 vector; /**< Spurious Vector. */ |
169 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */ |
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170 | unsigned focus_checking : 1; /**< Focus Processor Checking. */ |
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513 | jermar | 171 | unsigned : 22; /**< Reserved. */ |
172 | } __attribute__ ((packed)); |
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173 | }; |
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174 | typedef union svr svr_t; |
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1 | jermar | 175 | |
514 | jermar | 176 | /** Time Divide Configuration Register. */ |
1 | jermar | 177 | #define TDCR (0x3e0/sizeof(__u32)) |
514 | jermar | 178 | union tdcr { |
179 | __u32 value; |
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180 | struct { |
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181 | unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */ |
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182 | unsigned : 28; /**< Reserved. */ |
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183 | } __attribute__ ((packed)); |
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184 | }; |
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185 | typedef union tdcr tdcr_t; |
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1 | jermar | 186 | |
187 | /* Initial Count Register for Timer */ |
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188 | #define ICRT (0x380/sizeof(__u32)) |
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189 | |||
190 | /* Current Count Register for Timer */ |
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191 | #define CCRT (0x390/sizeof(__u32)) |
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192 | |||
513 | jermar | 193 | /** LVT Timer register. */ |
1 | jermar | 194 | #define LVT_Tm (0x320/sizeof(__u32)) |
513 | jermar | 195 | union lvt_tm { |
196 | __u32 value; |
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197 | struct { |
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198 | __u8 vector; /**< Local Timer Interrupt vector. */ |
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199 | unsigned : 4; /**< Reserved. */ |
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200 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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201 | unsigned : 3; /**< Reserved. */ |
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202 | unsigned masked : 1; /**< Interrupt Mask. */ |
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203 | unsigned mode : 1; /**< Timer Mode. */ |
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204 | unsigned : 14; /**< Reserved. */ |
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205 | } __attribute__ ((packed)); |
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206 | }; |
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207 | typedef union lvt_tm lvt_tm_t; |
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208 | |||
209 | /** LVT LINT registers. */ |
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1 | jermar | 210 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
211 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
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513 | jermar | 212 | union lvt_lint { |
213 | __u32 value; |
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214 | struct { |
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215 | __u8 vector; /**< LINT Interrupt vector. */ |
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216 | unsigned delmod : 3; /**< Delivery Mode. */ |
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217 | unsigned : 1; /**< Reserved. */ |
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218 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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219 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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220 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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221 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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222 | unsigned masked : 1; /**< Interrupt Mask. */ |
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223 | unsigned : 15; /**< Reserved. */ |
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224 | } __attribute__ ((packed)); |
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225 | }; |
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226 | typedef union lvt_lint lvt_lint_t; |
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227 | |||
228 | /** LVT Error register. */ |
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1 | jermar | 229 | #define LVT_Err (0x370/sizeof(__u32)) |
513 | jermar | 230 | union lvt_error { |
231 | __u32 value; |
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232 | struct { |
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233 | __u8 vector; /**< Local Timer Interrupt vector. */ |
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234 | unsigned : 4; /**< Reserved. */ |
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235 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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236 | unsigned : 3; /**< Reserved. */ |
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237 | unsigned masked : 1; /**< Interrupt Mask. */ |
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238 | unsigned : 15; /**< Reserved. */ |
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239 | } __attribute__ ((packed)); |
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240 | }; |
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241 | typedef union lvt_error lvt_error_t; |
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242 | |||
514 | jermar | 243 | /** Local APIC ID Register. */ |
1 | jermar | 244 | #define L_APIC_ID (0x020/sizeof(__u32)) |
515 | jermar | 245 | union l_apic_id { |
514 | jermar | 246 | __u32 value; |
247 | struct { |
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248 | unsigned : 24; /**< Reserved. */ |
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249 | __u8 apic_id; /**< Local APIC ID. */ |
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250 | } __attribute__ ((packed)); |
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251 | }; |
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515 | jermar | 252 | typedef union l_apic_id l_apic_id_t; |
1 | jermar | 253 | |
1251 | jermar | 254 | /** Local APIC Version Register */ |
27 | jermar | 255 | #define LAVR (0x030/sizeof(__u32)) |
256 | #define LAVR_Mask 0xff |
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257 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
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258 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
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259 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
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260 | |||
672 | jermar | 261 | /** Logical Destination Register. */ |
262 | #define LDR (0x0d0/sizeof(__u32)) |
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263 | union ldr { |
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264 | __u32 value; |
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265 | struct { |
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1251 | jermar | 266 | unsigned : 24; /**< Reserved. */ |
672 | jermar | 267 | __u8 id; /**< Logical APIC ID. */ |
268 | } __attribute__ ((packed)); |
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269 | }; |
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270 | typedef union ldr ldr_t; |
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271 | |||
272 | /** Destination Format Register. */ |
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273 | #define DFR (0x0e0/sizeof(__u32)) |
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274 | union dfr { |
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275 | __u32 value; |
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276 | struct { |
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277 | unsigned : 28; /**< Reserved, all ones. */ |
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278 | unsigned model : 4; /**< Model. */ |
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279 | } __attribute__ ((packed)); |
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280 | }; |
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281 | typedef union dfr dfr_t; |
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282 | |||
1 | jermar | 283 | /* IO APIC */ |
284 | #define IOREGSEL (0x00/sizeof(__u32)) |
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285 | #define IOWIN (0x10/sizeof(__u32)) |
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286 | |||
287 | #define IOAPICID 0x00 |
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288 | #define IOAPICVER 0x01 |
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289 | #define IOAPICARB 0x02 |
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290 | #define IOREDTBL 0x10 |
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291 | |||
514 | jermar | 292 | /** I/O Register Select Register. */ |
293 | union io_regsel { |
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294 | __u32 value; |
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295 | struct { |
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296 | __u8 reg_addr; /**< APIC Register Address. */ |
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297 | unsigned : 24; /**< Reserved. */ |
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298 | } __attribute__ ((packed)); |
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299 | }; |
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300 | typedef union io_regsel io_regsel_t; |
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301 | |||
512 | jermar | 302 | /** I/O Redirection Register. */ |
303 | struct io_redirection_reg { |
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304 | union { |
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305 | __u32 lo; |
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306 | struct { |
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513 | jermar | 307 | __u8 intvec; /**< Interrupt Vector. */ |
512 | jermar | 308 | unsigned delmod : 3; /**< Delivery Mode. */ |
309 | unsigned destmod : 1; /**< Destination mode. */ |
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310 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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311 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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312 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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313 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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314 | unsigned masked : 1; /**< Interrupt Mask. */ |
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315 | unsigned : 15; /**< Reserved. */ |
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513 | jermar | 316 | } __attribute__ ((packed)); |
512 | jermar | 317 | }; |
318 | union { |
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319 | __u32 hi; |
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320 | struct { |
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321 | unsigned : 24; /**< Reserved. */ |
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1251 | jermar | 322 | __u8 dest : 8; /**< Destination Field. */ |
513 | jermar | 323 | } __attribute__ ((packed)); |
512 | jermar | 324 | }; |
325 | |||
326 | } __attribute__ ((packed)); |
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327 | typedef struct io_redirection_reg io_redirection_reg_t; |
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328 | |||
515 | jermar | 329 | |
330 | /** IO APIC Identification Register. */ |
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331 | union io_apic_id { |
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332 | __u32 value; |
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333 | struct { |
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334 | unsigned : 24; /**< Reserved. */ |
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335 | unsigned apic_id : 4; /**< IO APIC ID. */ |
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336 | unsigned : 4; /**< Reserved. */ |
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337 | } __attribute__ ((packed)); |
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338 | }; |
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339 | typedef union io_apic_id io_apic_id_t; |
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340 | |||
1 | jermar | 341 | extern volatile __u32 *l_apic; |
342 | extern volatile __u32 *io_apic; |
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343 | |||
344 | extern __u32 apic_id_mask; |
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345 | |||
346 | extern void apic_init(void); |
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347 | |||
348 | extern void l_apic_init(void); |
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349 | extern void l_apic_eoi(void); |
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5 | jermar | 350 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
1 | jermar | 351 | extern int l_apic_send_init_ipi(__u8 apicid); |
352 | extern void l_apic_debug(void); |
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81 | jermar | 353 | extern __u8 l_apic_id(void); |
1 | jermar | 354 | |
355 | extern __u32 io_apic_read(__u8 address); |
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356 | extern void io_apic_write(__u8 address , __u32 x); |
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514 | jermar | 357 | extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags); |
1 | jermar | 358 | extern void io_apic_disable_irqs(__u16 irqmask); |
359 | extern void io_apic_enable_irqs(__u16 irqmask); |
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360 | |||
361 | #endif |