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173 | jermar | 1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #ifndef __amd64_ASM_H__ |
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30 | #define __amd64_ASM_H__ |
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31 | |||
1186 | jermar | 32 | #include <arch/pm.h> |
173 | jermar | 33 | #include <arch/types.h> |
34 | #include <config.h> |
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35 | |||
597 | jermar | 36 | extern void asm_delay_loop(__u32 t); |
37 | extern void asm_fake_loop(__u32 t); |
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200 | palkovsky | 38 | |
253 | jermar | 39 | /** Return base address of current stack. |
40 | * |
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41 | * Return the base address of the current stack. |
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42 | * The stack is assumed to be STACK_SIZE bytes long. |
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43 | * The stack must start on page boundary. |
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44 | */ |
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173 | jermar | 45 | static inline __address get_stack_base(void) |
46 | { |
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226 | palkovsky | 47 | __address v; |
48 | |||
49 | __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1))); |
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50 | |||
51 | return v; |
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173 | jermar | 52 | } |
53 | |||
348 | jermar | 54 | static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); }; |
55 | static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); }; |
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197 | palkovsky | 56 | |
200 | palkovsky | 57 | |
625 | palkovsky | 58 | /** Byte from port |
59 | * |
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60 | * Get byte from port |
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61 | * |
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62 | * @param port Port to read from |
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63 | * @return Value read |
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64 | */ |
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65 | static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
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200 | palkovsky | 66 | |
625 | palkovsky | 67 | /** Byte to port |
68 | * |
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69 | * Output byte to port |
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70 | * |
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71 | * @param port Port to write to |
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72 | * @param val Value to write |
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73 | */ |
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74 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
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200 | palkovsky | 75 | |
806 | palkovsky | 76 | /** Swap Hidden part of GS register with visible one */ |
77 | static inline void swapgs(void) { __asm__ volatile("swapgs"); } |
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78 | |||
413 | jermar | 79 | /** Enable interrupts. |
200 | palkovsky | 80 | * |
81 | * Enable interrupts and return previous |
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82 | * value of EFLAGS. |
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413 | jermar | 83 | * |
84 | * @return Old interrupt priority level. |
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200 | palkovsky | 85 | */ |
413 | jermar | 86 | static inline ipl_t interrupts_enable(void) { |
87 | ipl_t v; |
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200 | palkovsky | 88 | __asm__ volatile ( |
89 | "pushfq\n" |
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90 | "popq %0\n" |
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91 | "sti\n" |
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92 | : "=r" (v) |
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93 | ); |
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94 | return v; |
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95 | } |
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96 | |||
413 | jermar | 97 | /** Disable interrupts. |
200 | palkovsky | 98 | * |
99 | * Disable interrupts and return previous |
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100 | * value of EFLAGS. |
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413 | jermar | 101 | * |
102 | * @return Old interrupt priority level. |
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200 | palkovsky | 103 | */ |
413 | jermar | 104 | static inline ipl_t interrupts_disable(void) { |
105 | ipl_t v; |
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200 | palkovsky | 106 | __asm__ volatile ( |
107 | "pushfq\n" |
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108 | "popq %0\n" |
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109 | "cli\n" |
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110 | : "=r" (v) |
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111 | ); |
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112 | return v; |
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113 | } |
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114 | |||
413 | jermar | 115 | /** Restore interrupt priority level. |
200 | palkovsky | 116 | * |
117 | * Restore EFLAGS. |
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413 | jermar | 118 | * |
119 | * @param ipl Saved interrupt priority level. |
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200 | palkovsky | 120 | */ |
413 | jermar | 121 | static inline void interrupts_restore(ipl_t ipl) { |
200 | palkovsky | 122 | __asm__ volatile ( |
123 | "pushq %0\n" |
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124 | "popfq\n" |
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413 | jermar | 125 | : : "r" (ipl) |
200 | palkovsky | 126 | ); |
127 | } |
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128 | |||
413 | jermar | 129 | /** Return interrupt priority level. |
206 | palkovsky | 130 | * |
131 | * Return EFLAFS. |
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413 | jermar | 132 | * |
133 | * @return Current interrupt priority level. |
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206 | palkovsky | 134 | */ |
413 | jermar | 135 | static inline ipl_t interrupts_read(void) { |
136 | ipl_t v; |
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206 | palkovsky | 137 | __asm__ volatile ( |
138 | "pushfq\n" |
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139 | "popq %0\n" |
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140 | : "=r" (v) |
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141 | ); |
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142 | return v; |
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143 | } |
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200 | palkovsky | 144 | |
803 | palkovsky | 145 | /** Write to MSR */ |
146 | static inline void write_msr(__u32 msr, __u64 value) |
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147 | { |
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148 | __asm__ volatile ( |
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149 | "wrmsr;" : : "c" (msr), |
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150 | "a" ((__u32)(value)), |
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151 | "d" ((__u32)(value >> 32)) |
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152 | ); |
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153 | } |
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219 | palkovsky | 154 | |
803 | palkovsky | 155 | static inline __native read_msr(__u32 msr) |
156 | { |
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157 | __u32 ax, dx; |
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158 | |||
159 | __asm__ volatile ( |
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160 | "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr) |
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161 | ); |
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162 | return ((__u64)dx << 32) | ax; |
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163 | } |
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164 | |||
165 | |||
268 | palkovsky | 166 | /** Enable local APIC |
167 | * |
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168 | * Enable local APIC in MSR. |
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169 | */ |
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170 | static inline void enable_l_apic_in_msr() |
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171 | { |
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172 | __asm__ volatile ( |
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348 | jermar | 173 | "movl $0x1b, %%ecx\n" |
174 | "rdmsr\n" |
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175 | "orl $(1<<11),%%eax\n" |
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176 | "orl $(0xfee00000),%%eax\n" |
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177 | "wrmsr\n" |
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268 | palkovsky | 178 | : |
179 | : |
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180 | :"%eax","%ecx","%edx" |
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181 | ); |
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182 | } |
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183 | |||
581 | palkovsky | 184 | static inline __address * get_ip() |
185 | { |
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186 | __address *ip; |
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187 | |||
188 | __asm__ volatile ( |
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189 | "mov %%rip, %0" |
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190 | : "=r" (ip) |
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191 | ); |
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192 | return ip; |
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193 | } |
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194 | |||
597 | jermar | 195 | /** Invalidate TLB Entry. |
196 | * |
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197 | * @param addr Address on a page whose TLB entry is to be invalidated. |
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198 | */ |
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199 | static inline void invlpg(__address addr) |
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200 | { |
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1186 | jermar | 201 | __asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr))); |
597 | jermar | 202 | } |
581 | palkovsky | 203 | |
1186 | jermar | 204 | /** Load GDTR register from memory. |
205 | * |
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206 | * @param gdtr_reg Address of memory from where to load GDTR. |
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207 | */ |
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208 | static inline void gdtr_load(struct ptr_16_64 *gdtr_reg) |
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209 | { |
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1251 | jermar | 210 | __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg)); |
1186 | jermar | 211 | } |
212 | |||
213 | /** Store GDTR register to memory. |
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214 | * |
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215 | * @param gdtr_reg Address of memory to where to load GDTR. |
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216 | */ |
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217 | static inline void gdtr_store(struct ptr_16_64 *gdtr_reg) |
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218 | { |
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1251 | jermar | 219 | __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg)); |
1186 | jermar | 220 | } |
221 | |||
222 | /** Load IDTR register from memory. |
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223 | * |
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224 | * @param idtr_reg Address of memory from where to load IDTR. |
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225 | */ |
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226 | static inline void idtr_load(struct ptr_16_64 *idtr_reg) |
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227 | { |
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1251 | jermar | 228 | __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg)); |
1186 | jermar | 229 | } |
230 | |||
231 | /** Load TR from descriptor table. |
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232 | * |
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233 | * @param sel Selector specifying descriptor of TSS segment. |
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234 | */ |
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235 | static inline void tr_load(__u16 sel) |
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236 | { |
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237 | __asm__ volatile ("ltr %0" : : "r" (sel)); |
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238 | } |
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239 | |||
1072 | palkovsky | 240 | #define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \ |
241 | { \ |
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242 | __native res; \ |
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243 | __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \ |
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244 | return res; \ |
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245 | } |
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246 | |||
247 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \ |
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248 | { \ |
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249 | __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \ |
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250 | } |
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251 | |||
252 | GEN_READ_REG(cr0); |
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253 | GEN_READ_REG(cr2); |
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254 | GEN_READ_REG(cr3); |
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255 | GEN_WRITE_REG(cr3); |
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256 | |||
257 | GEN_READ_REG(dr0); |
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258 | GEN_READ_REG(dr1); |
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259 | GEN_READ_REG(dr2); |
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260 | GEN_READ_REG(dr3); |
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261 | GEN_READ_REG(dr6); |
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262 | GEN_READ_REG(dr7); |
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263 | |||
264 | GEN_WRITE_REG(dr0); |
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265 | GEN_WRITE_REG(dr1); |
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266 | GEN_WRITE_REG(dr2); |
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267 | GEN_WRITE_REG(dr3); |
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268 | GEN_WRITE_REG(dr6); |
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269 | GEN_WRITE_REG(dr7); |
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270 | |||
271 | |||
206 | palkovsky | 272 | extern size_t interrupt_handler_size; |
273 | extern void interrupt_handlers(void); |
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274 | |||
173 | jermar | 275 | #endif |