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1 | jermar | 1 | # |
319 | jermar | 2 | # Copyright (C) 2003-2004 Jakub Jermar |
1 | jermar | 3 | # All rights reserved. |
4 | # |
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5 | # Redistribution and use in source and binary forms, with or without |
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6 | # modification, are permitted provided that the following conditions |
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7 | # are met: |
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8 | # |
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9 | # - Redistributions of source code must retain the above copyright |
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10 | # notice, this list of conditions and the following disclaimer. |
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11 | # - Redistributions in binary form must reproduce the above copyright |
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12 | # notice, this list of conditions and the following disclaimer in the |
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13 | # documentation and/or other materials provided with the distribution. |
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14 | # - The name of the author may not be used to endorse or promote products |
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15 | # derived from this software without specific prior written permission. |
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16 | # |
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17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | # |
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28 | |||
326 | palkovsky | 29 | #include <arch/asm/regname.h> |
30 | |||
1 | jermar | 31 | .text |
32 | |||
33 | .macro cp0_read reg |
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50 | jermar | 34 | mfc0 $2,\reg |
35 | j $31 |
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36 | nop |
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1 | jermar | 37 | .endm |
38 | |||
39 | .macro cp0_write reg |
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50 | jermar | 40 | mtc0 $4,\reg |
41 | j $31 |
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42 | nop |
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1 | jermar | 43 | .endm |
44 | |||
45 | .set noat |
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46 | .set noreorder |
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47 | .set nomacro |
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48 | |||
49 | .global cpu_halt |
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50 | cpu_halt: |
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51 | j cpu_halt |
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52 | nop |
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53 | |||
54 | |||
59 | jermar | 55 | .global memsetb |
56 | memsetb: |
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57 | j _memsetb |
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58 | nop |
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59 | |||
1288 | jermar | 60 | |
205 | jermar | 61 | .global memcpy |
1288 | jermar | 62 | .global memcpy_from_uspace |
63 | .global memcpy_to_uspace |
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64 | .global memcpy_from_uspace_failover_address |
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65 | .global memcpy_to_uspace_failover_address |
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205 | jermar | 66 | memcpy: |
1288 | jermar | 67 | memcpy_from_uspace: |
68 | memcpy_to_uspace: |
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1293 | palkovsky | 69 | srl $t1,$a2,0x2 |
70 | beqz $t1,1f |
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71 | move $t0,$zero |
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72 | move $a3,$zero |
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73 | 2: |
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74 | addu $v0,$a1,$a3 |
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75 | lw $v1,0($v0) |
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76 | addiu $t0,$t0,1 |
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77 | addu $v0,$a0,$a3 |
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78 | sw $v1,0($v0) |
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79 | bne $t0,$t1,2b |
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80 | addiu $a3,$a3,4 |
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81 | 1: |
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82 | andi $a2,$a2,0x3 |
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83 | beqz $a2,3f |
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84 | move $a3,$zero |
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85 | sll $v0,$t0,0x2 |
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86 | addu $t1,$a0,$v0 |
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87 | addu $t0,$v0,$a1 |
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88 | 4: |
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89 | addu $v0,$t0,$a3 |
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90 | lbu $a0,0($v0) |
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91 | addu $v1,$t1,$a3 |
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92 | addiu $a3,$a3,1 |
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93 | bne $a3,$a2,4b |
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94 | sb $a0,0($v1) |
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95 | 3: |
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96 | jr $ra |
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97 | move $v0,$a1 |
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105 | jermar | 98 | |
1288 | jermar | 99 | memcpy_from_uspace_failover_address: |
100 | memcpy_to_uspace_failover_address: |
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1293 | palkovsky | 101 | jr $ra |
102 | move $v0, $zero |
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1288 | jermar | 103 | |
104 | |||
105 | |||
326 | palkovsky | 106 | .macro fpu_gp_save reg ctx |
107 | mfc1 $t0,$\reg |
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108 | sw $t0, \reg*4(\ctx) |
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109 | .endm |
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110 | |||
111 | .macro fpu_gp_restore reg ctx |
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112 | lw $t0, \reg*4(\ctx) |
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113 | mtc1 $t0,$\reg |
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114 | .endm |
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115 | |||
116 | .macro fpu_ct_save reg ctx |
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117 | cfc1 $t0,$1 |
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118 | sw $t0, (\reg+32)*4(\ctx) |
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119 | .endm |
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120 | |||
121 | .macro fpu_ct_restore reg ctx |
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122 | lw $t0, (\reg+32)*4(\ctx) |
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123 | ctc1 $t0,$\reg |
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124 | .endm |
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125 | |||
126 | |||
127 | .global fpu_context_save |
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128 | fpu_context_save: |
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924 | palkovsky | 129 | #ifdef ARCH_HAS_FPU |
326 | palkovsky | 130 | fpu_gp_save 0,$a0 |
131 | fpu_gp_save 1,$a0 |
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132 | fpu_gp_save 2,$a0 |
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133 | fpu_gp_save 3,$a0 |
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134 | fpu_gp_save 4,$a0 |
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135 | fpu_gp_save 5,$a0 |
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136 | fpu_gp_save 6,$a0 |
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137 | fpu_gp_save 7,$a0 |
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138 | fpu_gp_save 8,$a0 |
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139 | fpu_gp_save 9,$a0 |
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140 | fpu_gp_save 10,$a0 |
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141 | fpu_gp_save 11,$a0 |
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142 | fpu_gp_save 12,$a0 |
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143 | fpu_gp_save 13,$a0 |
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144 | fpu_gp_save 14,$a0 |
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145 | fpu_gp_save 15,$a0 |
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146 | fpu_gp_save 16,$a0 |
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147 | fpu_gp_save 17,$a0 |
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148 | fpu_gp_save 18,$a0 |
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149 | fpu_gp_save 19,$a0 |
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150 | fpu_gp_save 20,$a0 |
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151 | fpu_gp_save 21,$a0 |
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152 | fpu_gp_save 22,$a0 |
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153 | fpu_gp_save 23,$a0 |
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154 | fpu_gp_save 24,$a0 |
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155 | fpu_gp_save 25,$a0 |
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156 | fpu_gp_save 26,$a0 |
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157 | fpu_gp_save 27,$a0 |
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158 | fpu_gp_save 28,$a0 |
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159 | fpu_gp_save 29,$a0 |
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160 | fpu_gp_save 30,$a0 |
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161 | fpu_gp_save 31,$a0 |
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162 | |||
163 | fpu_ct_save 1,$a0 |
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164 | fpu_ct_save 2,$a0 |
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165 | fpu_ct_save 3,$a0 |
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166 | fpu_ct_save 4,$a0 |
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167 | fpu_ct_save 5,$a0 |
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168 | fpu_ct_save 6,$a0 |
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169 | fpu_ct_save 7,$a0 |
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170 | fpu_ct_save 8,$a0 |
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171 | fpu_ct_save 9,$a0 |
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172 | fpu_ct_save 10,$a0 |
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173 | fpu_ct_save 11,$a0 |
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174 | fpu_ct_save 12,$a0 |
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175 | fpu_ct_save 13,$a0 |
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176 | fpu_ct_save 14,$a0 |
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177 | fpu_ct_save 15,$a0 |
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178 | fpu_ct_save 16,$a0 |
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179 | fpu_ct_save 17,$a0 |
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180 | fpu_ct_save 18,$a0 |
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181 | fpu_ct_save 19,$a0 |
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182 | fpu_ct_save 20,$a0 |
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183 | fpu_ct_save 21,$a0 |
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184 | fpu_ct_save 22,$a0 |
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185 | fpu_ct_save 23,$a0 |
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186 | fpu_ct_save 24,$a0 |
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187 | fpu_ct_save 25,$a0 |
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188 | fpu_ct_save 26,$a0 |
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189 | fpu_ct_save 27,$a0 |
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190 | fpu_ct_save 28,$a0 |
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191 | fpu_ct_save 29,$a0 |
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192 | fpu_ct_save 30,$a0 |
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193 | fpu_ct_save 31,$a0 |
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194 | #endif |
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195 | j $ra |
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196 | nop |
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197 | |||
198 | .global fpu_context_restore |
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199 | fpu_context_restore: |
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924 | palkovsky | 200 | #ifdef ARCH_HAS_FPU |
326 | palkovsky | 201 | fpu_gp_restore 0,$a0 |
202 | fpu_gp_restore 1,$a0 |
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203 | fpu_gp_restore 2,$a0 |
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204 | fpu_gp_restore 3,$a0 |
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205 | fpu_gp_restore 4,$a0 |
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206 | fpu_gp_restore 5,$a0 |
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207 | fpu_gp_restore 6,$a0 |
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208 | fpu_gp_restore 7,$a0 |
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209 | fpu_gp_restore 8,$a0 |
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210 | fpu_gp_restore 9,$a0 |
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211 | fpu_gp_restore 10,$a0 |
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212 | fpu_gp_restore 11,$a0 |
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213 | fpu_gp_restore 12,$a0 |
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214 | fpu_gp_restore 13,$a0 |
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215 | fpu_gp_restore 14,$a0 |
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216 | fpu_gp_restore 15,$a0 |
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217 | fpu_gp_restore 16,$a0 |
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218 | fpu_gp_restore 17,$a0 |
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219 | fpu_gp_restore 18,$a0 |
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220 | fpu_gp_restore 19,$a0 |
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221 | fpu_gp_restore 20,$a0 |
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222 | fpu_gp_restore 21,$a0 |
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223 | fpu_gp_restore 22,$a0 |
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224 | fpu_gp_restore 23,$a0 |
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225 | fpu_gp_restore 24,$a0 |
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226 | fpu_gp_restore 25,$a0 |
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227 | fpu_gp_restore 26,$a0 |
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228 | fpu_gp_restore 27,$a0 |
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229 | fpu_gp_restore 28,$a0 |
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230 | fpu_gp_restore 29,$a0 |
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231 | fpu_gp_restore 30,$a0 |
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232 | fpu_gp_restore 31,$a0 |
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233 | |||
234 | fpu_ct_restore 1,$a0 |
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235 | fpu_ct_restore 2,$a0 |
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236 | fpu_ct_restore 3,$a0 |
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237 | fpu_ct_restore 4,$a0 |
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238 | fpu_ct_restore 5,$a0 |
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239 | fpu_ct_restore 6,$a0 |
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240 | fpu_ct_restore 7,$a0 |
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241 | fpu_ct_restore 8,$a0 |
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242 | fpu_ct_restore 9,$a0 |
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243 | fpu_ct_restore 10,$a0 |
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244 | fpu_ct_restore 11,$a0 |
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245 | fpu_ct_restore 12,$a0 |
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246 | fpu_ct_restore 13,$a0 |
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247 | fpu_ct_restore 14,$a0 |
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248 | fpu_ct_restore 15,$a0 |
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249 | fpu_ct_restore 16,$a0 |
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250 | fpu_ct_restore 17,$a0 |
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251 | fpu_ct_restore 18,$a0 |
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252 | fpu_ct_restore 19,$a0 |
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253 | fpu_ct_restore 20,$a0 |
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254 | fpu_ct_restore 21,$a0 |
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255 | fpu_ct_restore 22,$a0 |
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256 | fpu_ct_restore 23,$a0 |
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257 | fpu_ct_restore 24,$a0 |
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258 | fpu_ct_restore 25,$a0 |
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259 | fpu_ct_restore 26,$a0 |
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260 | fpu_ct_restore 27,$a0 |
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261 | fpu_ct_restore 28,$a0 |
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262 | fpu_ct_restore 29,$a0 |
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263 | fpu_ct_restore 30,$a0 |
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264 | fpu_ct_restore 31,$a0 |
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265 | #endif |
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266 | j $ra |
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267 | nop |