Subversion Repositories HelenOS

Rev

Rev 1962 | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
173 jermar 1
/*
2
 * Copyright (C) 2005 Jakub Jermar
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
29
#ifndef __ia64_ASM_H__
30
#define __ia64_ASM_H__
31
 
32
#include <arch/types.h>
33
#include <config.h>
432 jermar 34
#include <arch/register.h>
173 jermar 35
 
180 jermar 36
/** Return base address of current stack
37
 *
38
 * Return the base address of the current stack.
39
 * The stack is assumed to be STACK_SIZE long.
40
 * The stack must start on page boundary.
41
 */
173 jermar 42
static inline __address get_stack_base(void)
43
{
180 jermar 44
    __u64 v;
45
 
46
    __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
47
 
48
    return v;
173 jermar 49
}
50
 
432 jermar 51
/** Read IVR (External Interrupt Vector Register).
431 jermar 52
 *
53
 * @return Highest priority, pending, unmasked external interrupt vector.
54
 */
432 jermar 55
static inline __u64 ivr_read(void)
431 jermar 56
{
57
    __u64 v;
58
 
432 jermar 59
    __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v));
431 jermar 60
 
432 jermar 61
    return v;
431 jermar 62
}
195 vana 63
 
432 jermar 64
/** Write ITC (Interval Timer Counter) register.
65
 *
66
 * @param New counter value.
67
 */
68
static inline void itc_write(__u64 v)
69
{
70
    __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v));
71
}
431 jermar 72
 
432 jermar 73
/** Read ITC (Interval Timer Counter) register.
74
 *
75
 * @return Current counter value.
76
 */
77
static inline __u64 itc_read(void)
78
{
79
    __u64 v;
80
 
81
    __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v));
82
 
83
    return v;
84
}
195 vana 85
 
432 jermar 86
/** Write ITM (Interval Timer Match) register.
87
 *
88
 * @param New match value.
89
 */
90
static inline void itm_write(__u64 v)
91
{
92
    __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v));
93
}
195 vana 94
 
433 jermar 95
/** Read ITV (Interval Timer Vector) register.
96
 *
97
 * @return Current vector and mask bit.
98
 */
99
static inline __u64 itv_read(void)
100
{
101
    __u64 v;
102
 
103
    __asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v));
104
 
105
    return v;
106
}
107
 
432 jermar 108
/** Write ITV (Interval Timer Vector) register.
109
 *
433 jermar 110
 * @param New vector and mask bit.
432 jermar 111
 */
112
static inline void itv_write(__u64 v)
113
{
114
    __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v));
115
}
238 vana 116
 
432 jermar 117
/** Write EOI (End Of Interrupt) register.
118
 *
119
 * @param This value is ignored.
120
 */
121
static inline void eoi_write(__u64 v)
122
{
123
    __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v));
124
}
125
 
126
/** Read TPR (Task Priority Register).
127
 *
128
 * @return Current value of TPR.
129
 */
130
static inline __u64 tpr_read(void)
131
{
132
    __u64 v;
133
 
134
    __asm__ volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
135
 
136
    return v;
137
}
138
 
139
/** Write TPR (Task Priority Register).
140
 *
141
 * @param New value of TPR.
142
 */
143
static inline void tpr_write(__u64 v)
144
{
145
    __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v));
146
}
147
 
148
/** Disable interrupts.
149
 *
150
 * Disable interrupts and return previous
151
 * value of PSR.
152
 *
153
 * @return Old interrupt priority level.
154
 */
155
static ipl_t interrupts_disable(void)
156
{
157
    __u64 v;
158
 
159
    __asm__ volatile (
160
        "mov %0 = psr\n"
161
        "rsm %1\n"
162
        : "=r" (v)
163
        : "i" (PSR_I_MASK)
164
    );
165
 
166
    return (ipl_t) v;
167
}
168
 
169
/** Enable interrupts.
170
 *
171
 * Enable interrupts and return previous
172
 * value of PSR.
173
 *
174
 * @return Old interrupt priority level.
175
 */
176
static ipl_t interrupts_enable(void)
177
{
178
    __u64 v;
179
 
180
    __asm__ volatile (
181
        "mov %0 = psr\n"
182
        "ssm %1\n"
183
        ";;\n"
184
        "srlz.d\n"
185
        : "=r" (v)
186
        : "i" (PSR_I_MASK)
187
    );
188
 
189
    return (ipl_t) v;
190
}
191
 
192
/** Restore interrupt priority level.
193
 *
194
 * Restore PSR.
195
 *
196
 * @param ipl Saved interrupt priority level.
197
 */
198
static inline void interrupts_restore(ipl_t ipl)
199
{
200
    __asm__ volatile (
201
        "mov psr.l = %0\n"
202
        ";;\n"
203
        "srlz.d\n"
204
        : : "r" ((__u64) ipl)
205
    );
206
}
207
 
208
/** Return interrupt priority level.
209
 *
210
 * @return PSR.
211
 */
212
static inline ipl_t interrupts_read(void)
213
{
214
    __u64 v;
215
 
216
    __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
217
 
218
    return (ipl_t) v;
219
}
220
 
238 vana 221
#define set_shadow_register(reg,val) {__u64 v = val; __asm__  volatile("mov r15 = %0;;\n""bsw.0;;\n""mov "   #reg   " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); }
222
#define get_shadow_register(reg,val) {__u64 v ; __asm__  volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
223
 
224
#define get_control_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = cr" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
225
#define get_aplication_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
226
#define get_psr(val) {__u64 v ; __asm__  volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
227
 
432 jermar 228
extern void cpu_halt(void);
229
extern void cpu_sleep(void);
230
extern void asm_delay_loop(__u32 t);
238 vana 231
 
173 jermar 232
#endif