WebSVN – HelenOS-historic – Blame – /kernel/trunk/arch/sparc64/include/mm/tlb.h

Rev	Author	Line No.	Line
418	jermar	1	/*
		2	* Copyright (C) 2005 Jakub Jermar
		3	* All rights reserved.
		4	*
		5	* Redistribution and use in source and binary forms, with or without
		6	* modification, are permitted provided that the following conditions
		7	* are met:
		8	*
		9	* - Redistributions of source code must retain the above copyright
		10	* notice, this list of conditions and the following disclaimer.
		11	* - Redistributions in binary form must reproduce the above copyright
		12	* notice, this list of conditions and the following disclaimer in the
		13	* documentation and/or other materials provided with the distribution.
		14	* - The name of the author may not be used to endorse or promote products
		15	* derived from this software without specific prior written permission.
		16	*
		17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
		18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
		19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
		20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
		21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
		22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
		23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
		24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
		26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		27	*/
		28
		29	#ifndef __sparc64_TLB_H__
		30	#define __sparc64_TLB_H__
		31
530	jermar	32	#include <arch/mm/tte.h>
569	jermar	33	#include <arch/asm.h>
613	jermar	34	#include <arch/barrier.h>
569	jermar	35	#include <arch/types.h>
		36	#include <typedefs.h>
530	jermar	37
569	jermar	38	#define ITLB_ENTRY_COUNT 64
		39	#define DTLB_ENTRY_COUNT 64
		40
531	jermar	41	/** I-MMU ASIs. */
		42	#define ASI_IMMU 0x50
		43	#define ASI_IMMU_TSB_8KB_PTR_REG 0x51
		44	#define ASI_IMMU_TSB_64KB_PTR_REG 0x52
		45	#define ASI_ITLB_DATA_IN_REG 0x54
		46	#define ASI_ITLB_DATA_ACCESS_REG 0x55
		47	#define ASI_ITLB_TAG_READ_REG 0x56
		48	#define ASI_IMMU_DEMAP 0x57
		49
		50	/** Virtual Addresses within ASI_IMMU. */
		51	#define VA_IMMU_TAG_TARGET 0x0 /*< IMMU tag target register. /
		52	#define VA_IMMU_SFSR 0x18 /*< IMMU sync fault status register. /
		53	#define VA_IMMU_TSB_BASE 0x28 /*< IMMU TSB base register. /
		54	#define VA_IMMU_TAG_ACCESS 0x30 /*< IMMU TLB tag access register. /
		55
		56	/** D-MMU ASIs. */
		57	#define ASI_DMMU 0x58
		58	#define ASI_DMMU_TSB_8KB_PTR_REG 0x59
		59	#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
		60	#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
		61	#define ASI_DTLB_DATA_IN_REG 0x5c
		62	#define ASI_DTLB_DATA_ACCESS_REG 0x5d
		63	#define ASI_DTLB_TAG_READ_REG 0x5e
		64	#define ASI_DMMU_DEMAP 0x5f
		65
		66	/** Virtual Addresses within ASI_DMMU. */
		67	#define VA_DMMU_TAG_TARGET 0x0 /*< DMMU tag target register. /
		68	#define VA_PRIMARY_CONTEXT_REG 0x8 /*< DMMU primary context register. /
		69	#define VA_SECONDARY_CONTEXT_REG 0x10 /*< DMMU secondary context register. /
		70	#define VA_DMMU_SFSR 0x18 /*< DMMU sync fault status register. /
		71	#define VA_DMMU_SFAR 0x20 /*< DMMU sync fault address register. /
		72	#define VA_DMMU_TSB_BASE 0x28 /*< DMMU TSB base register. /
		73	#define VA_DMMU_TAG_ACCESS 0x30 /*< DMMU TLB tag access register. /
		74	#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /*< DMMU VA data watchpoint register. /
		75	#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /*< DMMU PA data watchpoint register. /
		76
530	jermar	77	/** I-/D-TLB Data In/Access Register type. */
		78	typedef tte_data_t tlb_data_t;
		79
569	jermar	80	/** I-/D-TLB Data Access Address in Alternate Space. */
		81	union tlb_data_access_addr {
		82	__u64 value;
		83	struct {
		84	__u64 : 55;
		85	unsigned tlb_entry : 6;
		86	unsigned : 3;
		87	} __attribute__ ((packed));
		88	};
		89	typedef union tlb_data_access_addr tlb_data_access_addr_t;
		90	typedef union tlb_data_access_addr tlb_tag_read_addr_t;
418	jermar	91
569	jermar	92	/** I-/D-TLB Tag Read Register. */
		93	union tlb_tag_read_reg {
		94	__u64 value;
		95	struct {
		96	__u64 va : 51; /*< Virtual Address. /
		97	unsigned context : 13; /*< Context identifier. /
		98	} __attribute__ ((packed));
		99	};
		100	typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
613	jermar	101	typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
569	jermar	102
		103	/** Read IMMU TLB Data Access Register.
		104	*
		105	* @param entry TLB Entry index.
		106	*
		107	* @return Current value of specified IMMU TLB Data Access Register.
		108	*/
		109	static inline __u64 itlb_data_access_read(index_t entry)
		110	{
		111	tlb_data_access_addr_t reg;
		112
		113	reg.value = 0;
		114	reg.tlb_entry = entry;
		115	return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
		116	}
		117
		118	/** Read DMMU TLB Data Access Register.
		119	*
		120	* @param entry TLB Entry index.
		121	*
		122	* @return Current value of specified DMMU TLB Data Access Register.
		123	*/
		124	static inline __u64 dtlb_data_access_read(index_t entry)
		125	{
		126	tlb_data_access_addr_t reg;
		127
		128	reg.value = 0;
		129	reg.tlb_entry = entry;
		130	return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
		131	}
		132
		133	/** Read IMMU TLB Tag Read Register.
		134	*
		135	* @param entry TLB Entry index.
		136	*
		137	* @return Current value of specified IMMU TLB Tag Read Register.
		138	*/
613	jermar	139	static inline __u64 itlb_tag_read_read(index_t entry)
569	jermar	140	{
		141	tlb_tag_read_addr_t tag;
		142
		143	tag.value = 0;
		144	tag.tlb_entry = entry;
		145	return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
		146	}
		147
		148	/** Read DMMU TLB Tag Read Register.
		149	*
		150	* @param entry TLB Entry index.
		151	*
		152	* @return Current value of specified DMMU TLB Tag Read Register.
		153	*/
613	jermar	154	static inline __u64 dtlb_tag_read_read(index_t entry)
569	jermar	155	{
		156	tlb_tag_read_addr_t tag;
		157
		158	tag.value = 0;
		159	tag.tlb_entry = entry;
		160	return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
		161	}
		162
613	jermar	163	/** Write IMMU TLB Tag Access Register.
		164	*
		165	* @param v Value to be written.
		166	*/
		167	static inline void itlb_tag_access_write(__u64 v)
		168	{
		169	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
		170	flush();
		171	}
		172
		173	/** Write DMMU TLB Tag Access Register.
		174	*
		175	* @param v Value to be written.
		176	*/
		177	static inline void dtlb_tag_access_write(__u64 v)
		178	{
		179	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
		180	flush();
		181	}
		182
		183	/** Write IMMU TLB Data in Register.
		184	*
		185	* @param v Value to be written.
		186	*/
		187	static inline void itlb_data_in_write(__u64 v)
		188	{
		189	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
		190	flush();
		191	}
		192
		193	/** Write DMMU TLB Data in Register.
		194	*
		195	* @param v Value to be written.
		196	*/
		197	static inline void dtlb_data_in_write(__u64 v)
		198	{
		199	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
		200	flush();
		201	}
		202
418	jermar	203	#endif

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