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| Rev | Author | Line No. | Line |
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| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | #include <arch/interrupt.h> |
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| 30 | #include <arch/types.h> |
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| 31 | #include <arch.h> |
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| 32 | #include <arch/cp0.h> |
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| 33 | #include <time/clock.h> |
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| 34 | #include <panic.h> |
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| 35 | |||
| 36 | pri_t cpu_priority_high(void) |
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| 37 | { |
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| 38 | pri_t pri = (pri_t) cp0_status_read(); |
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| 39 | cp0_status_write(pri & ~cp0_status_ie_enabled_bit); |
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| 40 | return pri; |
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| 41 | } |
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| 42 | |||
| 43 | pri_t cpu_priority_low(void) |
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| 44 | { |
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| 45 | pri_t pri = (pri_t) cp0_status_read(); |
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| 46 | cp0_status_write(pri | cp0_status_ie_enabled_bit); |
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| 47 | return pri; |
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| 48 | } |
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| 49 | |||
| 50 | void cpu_priority_restore(pri_t pri) |
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| 51 | { |
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| 52 | cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit)); |
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| 53 | } |
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| 54 | |||
| 55 | pri_t cpu_priority_read(void) |
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| 56 | { |
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| 57 | return cp0_status_read(); |
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| 58 | } |
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| 59 | |||
| 60 | |||
| 61 | void interrupt(void) |
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| 62 | { |
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| 63 | __u32 cause; |
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| 124 | decky | 64 | int i; |
| 65 | |||
| 1 | jermar | 66 | /* decode interrupt number and process the interrupt */ |
| 124 | decky | 67 | cause = (cp0_cause_read() >> 8) &0xff; |
| 68 | |||
| 69 | for (i = 0; i < 8; i++) { |
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| 70 | if (cause & (1 << i)) { |
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| 71 | switch (i) { |
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| 72 | case 0: /* SW0 - Software interrupt 0 */ |
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| 73 | cp0_cause_write(cause & ~(1 << 8)); /* clear SW0 interrupt */ |
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| 74 | break; |
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| 75 | case 1: /* SW1 - Software interrupt 1 */ |
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| 76 | cp0_cause_write(cause & ~(1 << 9)); /* clear SW1 interrupt */ |
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| 77 | break; |
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| 78 | case 2: /* IRQ0 */ |
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| 79 | case 3: /* IRQ1 */ |
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| 80 | case 4: /* IRQ2 */ |
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| 81 | case 5: /* IRQ3 */ |
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| 82 | case 6: /* IRQ4 */ |
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| 83 | panic("unhandled interrupt %d\n", i); |
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| 84 | break; |
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| 85 | case 7: /* Timer Interrupt */ |
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| 86 | cp0_compare_write(cp0_compare_value); /* clear timer interrupt */ |
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| 1 | jermar | 87 | /* start counting over again */ |
| 124 | decky | 88 | cp0_count_write(0); |
| 89 | clock(); |
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| 90 | break; |
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| 91 | } |
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| 92 | } |
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| 93 | } |
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| 1 | jermar | 94 | |
| 95 | } |