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| Rev | Author | Line No. | Line |
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| 740 | jermar | 1 | /* |
| 2 | * Copyright (C) 2006 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | /* |
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| 30 | * TLB management. |
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| 31 | */ |
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| 32 | |||
| 33 | #include <mm/tlb.h> |
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| 818 | vana | 34 | #include <arch/mm/tlb.h> |
| 740 | jermar | 35 | |
| 818 | vana | 36 | |
| 756 | jermar | 37 | /** Invalidate all TLB entries. */ |
| 740 | jermar | 38 | void tlb_invalidate_all(void) |
| 39 | { |
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| 40 | /* TODO */ |
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| 41 | } |
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| 42 | |||
| 43 | /** Invalidate entries belonging to an address space. |
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| 44 | * |
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| 45 | * @param asid Address space identifier. |
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| 46 | */ |
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| 47 | void tlb_invalidate_asid(asid_t asid) |
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| 48 | { |
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| 49 | /* TODO */ |
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| 50 | } |
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| 818 | vana | 51 | |
| 52 | |||
| 53 | |||
| 54 | void tlb_fill_data(__address va,asid_t asid,vhpt_entry_t entry) |
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| 55 | { |
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| 56 | region_register rr; |
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| 57 | |||
| 58 | |||
| 59 | if(!(entry.not_present.p)) return; |
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| 60 | |||
| 61 | rr.word=rr_read(VA_REGION(va)); |
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| 62 | |||
| 63 | if(rr.map.rid==ASID2RID(asid,VA_REGION(va))) |
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| 64 | { |
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| 65 | asm |
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| 66 | ( |
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| 67 | "srlz.i;;\n" |
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| 68 | "srlz.d;;\n" |
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| 69 | "mov r8=psr;;\n" |
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| 70 | "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ |
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| 71 | "mov psr.l=r9;;\n" |
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| 72 | "srlz.d;;\n" |
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| 73 | "srlz.i;;\n" |
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| 74 | "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/ |
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| 75 | "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/ |
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| 76 | "itc.d %3;;\n" /*entry.word[0]*/ |
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| 77 | "mov psr.l=r8;;\n" |
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| 78 | "srlz.d;;\n" |
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| 79 | : |
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| 80 | :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]) |
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| 81 | :"r8","r9" |
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| 82 | ); |
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| 83 | } |
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| 84 | else |
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| 85 | { |
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| 86 | region_register rr0; |
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| 87 | rr0=rr; |
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| 88 | rr0.map.rid=ASID2RID(asid,VA_REGION(va)); |
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| 89 | rr_write(VA_REGION(va),rr0.word); |
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| 90 | asm |
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| 91 | ( |
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| 92 | "mov r8=psr;;\n" |
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| 93 | "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ |
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| 94 | "mov psr.l=r9;;\n" |
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| 95 | "srlz.d;;\n" |
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| 96 | "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/ |
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| 97 | "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/ |
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| 98 | "itc.d %3;;\n" /*entry.word[0]*/ |
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| 99 | "mov psr.l=r8;;\n" |
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| 100 | "srlz.d;;\n" |
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| 101 | : |
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| 102 | :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]) |
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| 103 | :"r8","r9" |
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| 104 | ); |
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| 105 | rr_write(VA_REGION(va),rr.word); |
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| 106 | } |
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| 107 | |||
| 108 | |||
| 109 | } |
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| 110 | |||
| 111 | void tlb_fill_code(__address va,asid_t asid,vhpt_entry_t entry) |
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| 112 | { |
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| 113 | region_register rr; |
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| 114 | |||
| 115 | |||
| 116 | if(!(entry.not_present.p)) return; |
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| 117 | |||
| 118 | rr.word=rr_read(VA_REGION(va)); |
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| 119 | |||
| 120 | if(rr.map.rid==ASID2RID(asid,VA_REGION(va))) |
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| 121 | { |
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| 122 | asm |
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| 123 | ( |
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| 124 | "srlz.i;;\n" |
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| 125 | "srlz.d;;\n" |
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| 126 | "mov r8=psr;;\n" |
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| 127 | "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ |
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| 128 | "mov psr.l=r9;;\n" |
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| 129 | "srlz.d;;\n" |
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| 130 | "srlz.i;;\n" |
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| 131 | "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/ |
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| 132 | "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/ |
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| 133 | "itc.i %3;;\n" /*entry.word[0]*/ |
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| 134 | "mov psr.l=r8;;\n" |
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| 135 | "srlz.d;;\n" |
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| 136 | : |
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| 137 | :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]) |
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| 138 | :"r8","r9" |
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| 139 | ); |
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| 140 | } |
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| 141 | else |
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| 142 | { |
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| 143 | region_register rr0; |
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| 144 | rr0=rr; |
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| 145 | rr0.map.rid=ASID2RID(asid,VA_REGION(va)); |
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| 146 | rr_write(VA_REGION(va),rr0.word); |
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| 147 | asm |
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| 148 | ( |
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| 149 | "mov r8=psr;;\n" |
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| 150 | "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/ |
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| 151 | "mov psr.l=r9;;\n" |
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| 152 | "srlz.d;;\n" |
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| 153 | "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/ |
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| 154 | "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/ |
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| 155 | "itc.i %3;;\n" /*entry.word[0]*/ |
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| 156 | "mov psr.l=r8;;\n" |
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| 157 | "srlz.d;;\n" |
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| 158 | : |
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| 159 | :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0]) |
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| 160 | :"r8","r9" |
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| 161 | ); |
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| 162 | rr_write(VA_REGION(va),rr.word); |
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| 163 | } |
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| 164 | |||
| 165 | |||
| 166 | } |
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| 167 | |||
| 168 |