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Rev | Author | Line No. | Line |
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684 | jermar | 1 | /* |
2 | * Copyright (C) 2006 Jakub Jermar |
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747 | jermar | 3 | * Copyright (C) 2006 Jakub Vana |
684 | jermar | 4 | * All rights reserved. |
5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * |
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10 | * - Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * - Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * - The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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28 | */ |
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29 | |||
30 | #include <arch/mm/page.h> |
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747 | jermar | 31 | #include <genarch/mm/page_ht.h> |
32 | #include <mm/asid.h> |
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749 | jermar | 33 | #include <arch/mm/asid.h> |
716 | vana | 34 | #include <arch/types.h> |
749 | jermar | 35 | #include <typedefs.h> |
728 | vana | 36 | #include <print.h> |
684 | jermar | 37 | #include <mm/page.h> |
747 | jermar | 38 | #include <mm/frame.h> |
684 | jermar | 39 | #include <config.h> |
40 | #include <panic.h> |
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746 | jermar | 41 | #include <arch/asm.h> |
747 | jermar | 42 | #include <arch/barrier.h> |
748 | jermar | 43 | #include <memstr.h> |
684 | jermar | 44 | |
749 | jermar | 45 | static void set_vhpt_environment(void); |
46 | |||
47 | /** Initialize ia64 virtual address translation subsystem. */ |
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48 | void page_arch_init(void) |
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49 | { |
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50 | page_operations = &page_ht_operations; |
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51 | pk_disable(); |
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52 | set_vhpt_environment(); |
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53 | } |
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54 | |||
747 | jermar | 55 | /** Initialize VHPT and region registers. */ |
749 | jermar | 56 | void set_vhpt_environment(void) |
716 | vana | 57 | { |
747 | jermar | 58 | region_register rr; |
59 | pta_register pta; |
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60 | int i; |
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716 | vana | 61 | |
747 | jermar | 62 | /* |
63 | * First set up kernel region register. |
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64 | */ |
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65 | rr.word = rr_read(VRN_KERNEL); |
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66 | rr.map.ve = 0; /* disable VHPT walker */ |
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67 | rr.map.ps = PAGE_WIDTH; |
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68 | rr.map.rid = ASID_KERNEL; |
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69 | rr_write(VRN_KERNEL, rr.word); |
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70 | srlz_i(); |
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71 | srlz_d(); |
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716 | vana | 72 | |
747 | jermar | 73 | /* |
74 | * And invalidate the rest of region register. |
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75 | */ |
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76 | for(i = 0; i < REGION_REGISTERS; i++) { |
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77 | /* skip kernel rr */ |
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78 | if (i == VRN_KERNEL) |
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79 | continue; |
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728 | vana | 80 | |
747 | jermar | 81 | rr.word == rr_read(i); |
748 | jermar | 82 | rr.map.ve = 0; /* disable VHPT walker */ |
747 | jermar | 83 | rr.map.rid = ASID_INVALID; |
84 | rr_write(i, rr.word); |
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85 | srlz_i(); |
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86 | srlz_d(); |
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87 | } |
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726 | jermar | 88 | |
715 | vana | 89 | /* |
747 | jermar | 90 | * Allocate VHPT and invalidate all its entries. |
91 | */ |
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92 | page_ht = (pte_t *) frame_alloc(FRAME_KA, VHPT_WIDTH - FRAME_WIDTH, NULL); |
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748 | jermar | 93 | memsetb((__address) page_ht, VHPT_SIZE, 0); |
94 | ht_invalidate_all(); |
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715 | vana | 95 | |
747 | jermar | 96 | /* |
97 | * Set up PTA register. |
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98 | */ |
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99 | pta.word = pta_read(); |
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100 | pta.map.ve = 0; /* disable VHPT walker */ |
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101 | pta.map.vf = 1; /* large entry format */ |
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102 | pta.map.size = VHPT_WIDTH; |
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751 | jermar | 103 | pta.map.base = ((__address) page_ht) >> PTA_BASE_SHIFT; |
747 | jermar | 104 | pta_write(pta.word); |
105 | srlz_i(); |
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106 | srlz_d(); |
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107 | } |
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728 | vana | 108 | |
748 | jermar | 109 | /** Calculate address of collision chain from VPN and ASID. |
110 | * |
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749 | jermar | 111 | * Interrupts must be disabled. |
748 | jermar | 112 | * |
113 | * @param page Address of virtual page including VRN bits. |
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114 | * @param asid Address space identifier. |
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115 | * |
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116 | * @return Head of VHPT collision chain for page and asid. |
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117 | */ |
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118 | pte_t *vhpt_hash(__address page, asid_t asid) |
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119 | { |
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120 | region_register rr_save, rr; |
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749 | jermar | 121 | index_t vrn; |
122 | rid_t rid; |
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748 | jermar | 123 | pte_t *t; |
124 | |||
749 | jermar | 125 | vrn = page >> VRN_SHIFT; |
126 | rid = ASID2RID(asid, vrn); |
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127 | |||
128 | rr_save.word = rr_read(vrn); |
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129 | if (rr_save.map.rid == rid) { |
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130 | /* |
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131 | * The RID is already in place, compute thash and return. |
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132 | */ |
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133 | t = (pte_t *) thash(page); |
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134 | return t; |
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135 | } |
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136 | |||
137 | /* |
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138 | * The RID must be written to some region register. |
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139 | * To speed things up, register indexed by vrn is used. |
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140 | */ |
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748 | jermar | 141 | rr.word = rr_save.word; |
749 | jermar | 142 | rr.map.rid = rid; |
143 | rr_write(vrn, rr.word); |
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748 | jermar | 144 | srlz_i(); |
749 | jermar | 145 | t = (pte_t *) thash(page); |
146 | rr_write(vrn, rr_save.word); |
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748 | jermar | 147 | srlz_i(); |
148 | srlz_d(); |
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149 | |||
150 | return t; |
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151 | } |
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749 | jermar | 152 | |
153 | /** Compare ASID and VPN against PTE. |
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154 | * |
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155 | * Interrupts must be disabled. |
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156 | * |
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157 | * @param page Address of virtual page including VRN bits. |
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158 | * @param asid Address space identifier. |
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159 | * |
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160 | * @return True if page and asid match the page and asid of t, false otherwise. |
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161 | */ |
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162 | bool vhpt_compare(__address page, asid_t asid, pte_t *t) |
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163 | { |
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164 | region_register rr_save, rr; |
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165 | index_t vrn; |
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166 | rid_t rid; |
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167 | bool match; |
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168 | |||
169 | ASSERT(t); |
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170 | |||
171 | vrn = page >> VRN_SHIFT; |
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172 | rid = ASID2RID(asid, vrn); |
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173 | |||
174 | rr_save.word = rr_read(vrn); |
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175 | if (rr_save.map.rid == rid) { |
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176 | /* |
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177 | * The RID is already in place, compare ttag with t and return. |
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178 | */ |
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179 | return ttag(page) == t->present.tag.tag_word; |
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180 | } |
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181 | |||
182 | /* |
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183 | * The RID must be written to some region register. |
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184 | * To speed things up, register indexed by vrn is used. |
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185 | */ |
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186 | rr.word = rr_save.word; |
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187 | rr.map.rid = rid; |
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188 | rr_write(vrn, rr.word); |
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189 | srlz_i(); |
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190 | match = (ttag(page) == t->present.tag.tag_word); |
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191 | rr_write(vrn, rr_save.word); |
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192 | srlz_i(); |
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193 | srlz_d(); |
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194 | |||
195 | return match; |
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196 | } |
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197 | |||
198 | /** Set up one VHPT entry. |
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199 | * |
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200 | * @param t VHPT entry to be set up. |
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201 | * @param page Virtual address of the page mapped by the entry. |
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202 | * @param asid Address space identifier of the address space to which page belongs. |
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203 | * @param frame Physical address of the frame to wich page is mapped. |
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204 | * @param flags Different flags for the mapping. |
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205 | */ |
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206 | void vhpt_set_record(pte_t *t, __address page, asid_t asid, __address frame, int flags) |
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207 | { |
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208 | region_register rr_save, rr; |
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209 | index_t vrn; |
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210 | rid_t rid; |
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211 | __u64 tag; |
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212 | |||
213 | ASSERT(t); |
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214 | |||
215 | vrn = page >> VRN_SHIFT; |
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216 | rid = ASID2RID(asid, vrn); |
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217 | |||
218 | /* |
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219 | * Compute ttag. |
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220 | */ |
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221 | rr_save.word = rr_read(vrn); |
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222 | rr.word = rr_save.word; |
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223 | rr.map.rid = rid; |
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224 | rr_write(vrn, rr.word); |
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225 | srlz_i(); |
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226 | tag = ttag(page); |
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227 | rr_write(vrn, rr_save.word); |
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228 | srlz_i(); |
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229 | srlz_d(); |
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230 | |||
231 | /* |
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232 | * Clear the entry. |
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233 | */ |
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234 | t->word[0] = 0; |
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235 | t->word[1] = 0; |
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236 | t->word[2] = 0; |
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237 | t->word[3] = 0; |
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238 | |||
239 | t->present.p = true; |
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240 | t->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE; |
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241 | t->present.a = false; /* not accessed */ |
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242 | t->present.d = false; /* not dirty */ |
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243 | t->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL; |
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244 | t->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ; |
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245 | t->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0; |
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246 | t->present.ppn = frame >> PPN_SHIFT; |
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247 | t->present.ed = false; /* exception not deffered */ |
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248 | t->present.ps = PAGE_WIDTH; |
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249 | t->present.key = 0; |
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250 | t->present.tag.tag_word = tag; |
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251 | t->present.next = NULL; |
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252 | } |