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| Rev | Author | Line No. | Line |
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| 212 | vana | 1 | # |
| 2 | # Copyright (C) 2005 Jakub Vana |
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| 3 | # All rights reserved. |
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| 4 | # |
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| 5 | # Redistribution and use in source and binary forms, with or without |
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| 6 | # modification, are permitted provided that the following conditions |
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| 7 | # are met: |
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| 8 | # |
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| 9 | # - Redistributions of source code must retain the above copyright |
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| 10 | # notice, this list of conditions and the following disclaimer. |
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| 11 | # - Redistributions in binary form must reproduce the above copyright |
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| 12 | # notice, this list of conditions and the following disclaimer in the |
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| 13 | # documentation and/or other materials provided with the distribution. |
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| 14 | # - The name of the author may not be used to endorse or promote products |
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| 15 | # derived from this software without specific prior written permission. |
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| 16 | # |
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | # |
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| 28 | |||
| 29 | |||
| 438 | jermar | 30 | /** Heavyweight interrupt handler |
| 31 | * |
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| 435 | jermar | 32 | * This macro roughly follows steps from 1 to 19 described in |
| 33 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
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| 34 | * |
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| 438 | jermar | 35 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
| 36 | * This goal is achieved by using procedure calls after RSE becomes operational. |
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| 37 | * |
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| 435 | jermar | 38 | * Some steps are skipped (enabling and disabling interrupts). |
| 39 | * Some steps are not fully supported yet (e.g. interruptions |
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| 438 | jermar | 40 | * from userspace and floating-point context). |
| 435 | jermar | 41 | */ |
| 42 | .macro HEAVYWEIGHT_HANDLER offs handler |
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| 43 | .org IVT + \offs |
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| 212 | vana | 44 | |
| 435 | jermar | 45 | /* 1. copy interrupt registers into bank 0 */ |
| 46 | mov r24 = cr.iip |
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| 47 | mov r25 = cr.ipsr |
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| 48 | mov r26 = cr.iipa |
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| 49 | mov r27 = cr.isr |
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| 50 | mov r28 = cr.ifa |
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| 51 | |||
| 52 | /* 2. preserve predicate register into bank 0 */ |
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| 53 | mov r29 = pr ;; |
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| 54 | |||
| 438 | jermar | 55 | /* 3. switch to kernel memory stack */ |
| 435 | jermar | 56 | /* TODO: support interruptions from userspace */ |
| 57 | /* assume kernel stack */ |
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| 58 | |||
| 439 | jermar | 59 | /* 4. save registers in bank 0 into memory stack */ |
| 441 | jermar | 60 | add r12 = -8, r12 ;; |
| 61 | |||
| 435 | jermar | 62 | st8 [r12] = r29, -8 ;; /* save predicate registers */ |
| 438 | jermar | 63 | |
| 64 | st8 [r12] = r24, -8 ;; /* save cr.iip */ |
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| 65 | st8 [r12] = r25, -8 ;; /* save cr.ipsr */ |
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| 66 | st8 [r12] = r26, -8 ;; /* save cr.iipa */ |
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| 435 | jermar | 67 | st8 [r12] = r27, -8 ;; /* save cr.isr */ |
| 438 | jermar | 68 | st8 [r12] = r28, -8 ;; /* save cr.ifa */ |
| 69 | |||
| 70 | /* 5. RSE switch from interrupted context */ |
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| 435 | jermar | 71 | .auto |
| 72 | mov r24 = ar.rsc |
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| 73 | mov r25 = ar.pfs |
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| 74 | cover |
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| 75 | mov r26 = cr.ifs |
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| 76 | |||
| 77 | st8 [r12] = r24, -8 /* save ar.rsc */ |
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| 78 | st8 [r12] = r25, -8 /* save ar.pfs */ |
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| 79 | st8 [r12] = r26, -8 /* save ar.ifs */ |
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| 80 | |||
| 81 | and r30 = ~3, r24 |
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| 82 | mov ar.rsc = r30 /* place RSE in enforced lazy mode */ |
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| 83 | |||
| 84 | mov r27 = ar.rnat |
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| 85 | mov r28 = ar.bspstore |
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| 86 | |||
| 87 | /* assume kernel backing store */ |
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| 88 | mov ar.bspstore = r28 |
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| 89 | |||
| 90 | mov r29 = ar.bsp |
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| 91 | |||
| 92 | st8 [r12] = r27, -8 /* save ar.rnat */ |
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| 93 | st8 [r12] = r28, -8 /* save ar.bspstore */ |
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| 442 | vana | 94 | st8 [r12] = r29 /* save ar.bsp */ |
| 435 | jermar | 95 | |
| 96 | mov ar.rsc = r24 /* restore RSE's setting */ |
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| 97 | .explicit |
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| 98 | |||
| 438 | jermar | 99 | /* the rest of the save-handler can be kept outside IVT */ |
| 100 | |||
| 101 | movl r24 = \handler |
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| 102 | mov r25 = b0 |
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| 103 | br.call.sptk.many rp = heavyweight_handler_inner |
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| 104 | 0: mov b0 = r25 |
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| 105 | |||
| 439 | jermar | 106 | br heavyweight_handler_finalize |
| 438 | jermar | 107 | .endm |
| 108 | |||
| 109 | .global heavyweight_handler_inner |
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| 110 | heavyweight_handler_inner: |
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| 111 | /* |
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| 112 | * From this point, the rest of the interrupted context |
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| 113 | * will be preserved in stacked registers and backing store. |
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| 114 | */ |
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| 115 | alloc loc0 = ar.pfs, 0, 46, 0, 0 ;; |
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| 116 | |||
| 117 | /* copy handler address (r24 from bank 0 will be invisible soon) */ |
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| 118 | mov loc1 = r24 |
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| 119 | |||
| 435 | jermar | 120 | /* 6. switch to bank 1 and reenable PSR.ic */ |
| 121 | ssm 0x2000 |
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| 122 | bsw.1 ;; |
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| 123 | srlz.d |
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| 124 | |||
| 125 | /* 7. preserve branch and application registers */ |
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| 438 | jermar | 126 | mov loc2 = ar.unat |
| 127 | mov loc3 = ar.lc |
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| 128 | mov loc4 = ar.ec |
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| 129 | mov loc5 = ar.ccv |
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| 130 | mov loc6 = ar.csd |
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| 131 | mov loc7 = ar.ssd |
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| 435 | jermar | 132 | |
| 438 | jermar | 133 | mov loc8 = b0 |
| 134 | mov loc9 = b1 |
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| 135 | mov loc10 = b2 |
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| 136 | mov loc11 = b3 |
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| 137 | mov loc12 = b4 |
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| 138 | mov loc13 = b5 |
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| 139 | mov loc14 = b6 |
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| 140 | mov loc15 = b7 |
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| 141 | |||
| 435 | jermar | 142 | /* 8. preserve general and floating-point registers */ |
| 143 | /* TODO: save floating-point context */ |
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| 438 | jermar | 144 | mov loc16 = r1 |
| 145 | mov loc17 = r2 |
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| 146 | mov loc18 = r3 |
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| 147 | mov loc19 = r4 |
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| 148 | mov loc20 = r5 |
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| 149 | mov loc21 = r6 |
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| 150 | mov loc22 = r7 |
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| 151 | mov loc23 = r8 |
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| 152 | mov loc24 = r9 |
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| 153 | mov loc25 = r10 |
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| 154 | mov loc26 = r11 |
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| 155 | /* skip r12 (stack pointer) */ |
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| 156 | mov loc27 = r13 |
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| 157 | mov loc28 = r14 |
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| 158 | mov loc29 = r15 |
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| 159 | mov loc30 = r16 |
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| 160 | mov loc31 = r17 |
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| 161 | mov loc32 = r18 |
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| 162 | mov loc33 = r19 |
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| 163 | mov loc34 = r20 |
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| 164 | mov loc35 = r21 |
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| 165 | mov loc36 = r22 |
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| 166 | mov loc37 = r23 |
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| 167 | mov loc38 = r24 |
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| 168 | mov loc39 = r25 |
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| 169 | mov loc40 = r26 |
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| 170 | mov loc41 = r27 |
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| 171 | mov loc42 = r28 |
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| 172 | mov loc43 = r29 |
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| 173 | mov loc44 = r30 |
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| 174 | mov loc45 = r31 |
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| 175 | |||
| 435 | jermar | 176 | /* 9. skipped (will not enable interrupts) */ |
| 238 | vana | 177 | |
| 438 | jermar | 178 | /* 10. call handler */ |
| 179 | mov b1 = loc1 |
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| 180 | br.call.sptk.many b0 = b1 |
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| 181 | |||
| 182 | /* 11. return from handler */ |
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| 183 | 0: |
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| 184 | |||
| 435 | jermar | 185 | /* 12. skipped (will not disable interrupts) */ |
| 438 | jermar | 186 | |
| 435 | jermar | 187 | /* 13. restore general and floating-point registers */ |
| 188 | /* TODO: restore floating-point context */ |
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| 438 | jermar | 189 | mov r1 = loc16 |
| 190 | mov r2 = loc17 |
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| 191 | mov r3 = loc18 |
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| 192 | mov r4 = loc19 |
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| 193 | mov r5 = loc20 |
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| 194 | mov r6 = loc21 |
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| 195 | mov r7 = loc22 |
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| 196 | mov r8 = loc23 |
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| 197 | mov r9 = loc24 |
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| 198 | mov r10 = loc25 |
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| 199 | mov r11 = loc26 |
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| 200 | /* skip r12 (stack pointer) */ |
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| 201 | mov r13 = loc27 |
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| 202 | mov r14 = loc28 |
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| 203 | mov r15 = loc29 |
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| 204 | mov r16 = loc30 |
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| 205 | mov r17 = loc31 |
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| 206 | mov r18 = loc32 |
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| 207 | mov r19 = loc33 |
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| 208 | mov r20 = loc34 |
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| 209 | mov r21 = loc35 |
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| 210 | mov r22 = loc36 |
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| 211 | mov r23 = loc37 |
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| 212 | mov r24 = loc38 |
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| 213 | mov r25 = loc39 |
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| 214 | mov r26 = loc40 |
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| 215 | mov r27 = loc41 |
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| 216 | mov r28 = loc42 |
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| 217 | mov r29 = loc43 |
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| 218 | mov r30 = loc44 |
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| 219 | mov r31 = loc45 |
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| 435 | jermar | 220 | |
| 221 | /* 14. restore branch and application registers */ |
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| 438 | jermar | 222 | mov ar.unat = loc2 |
| 223 | mov ar.lc = loc3 |
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| 224 | mov ar.ec = loc4 |
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| 225 | mov ar.ccv = loc5 |
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| 226 | mov ar.csd = loc6 |
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| 227 | mov ar.ssd = loc7 |
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| 435 | jermar | 228 | |
| 438 | jermar | 229 | mov b0 = loc8 |
| 230 | mov b1 = loc9 |
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| 231 | mov b2 = loc10 |
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| 232 | mov b3 = loc11 |
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| 233 | mov b4 = loc12 |
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| 234 | mov b5 = loc13 |
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| 235 | mov b6 = loc14 |
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| 236 | mov b7 = loc15 |
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| 237 | |||
| 435 | jermar | 238 | /* 15. disable PSR.ic and switch to bank 0 */ |
| 239 | rsm 0x2000 |
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| 240 | bsw.0 ;; |
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| 241 | srlz.d |
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| 438 | jermar | 242 | |
| 243 | mov ar.pfs = loc0 |
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| 244 | br.ret.sptk.many rp |
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| 245 | |||
| 246 | .global heavyweight_handler_finalize |
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| 247 | heavyweight_handler_finalize: |
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| 248 | /* 16. RSE switch to interrupted context */ |
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| 435 | jermar | 249 | |
| 250 | /* 17. restore interruption state from memory stack */ |
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| 251 | |||
| 252 | /* 18. restore predicate registers from memory stack */ |
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| 253 | |||
| 254 | /* 19. return from interruption */ |
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| 255 | rfi |
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| 256 | |||
| 257 | |||
| 438 | jermar | 258 | |
| 259 | |||
| 238 | vana | 260 | dump_gregs: |
| 261 | mov r16 = REG_DUMP;; |
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| 262 | st8 [r16] = r0;; |
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| 263 | add r16 = 8,r16 ;; |
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| 264 | st8 [r16] = r1;; |
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| 265 | add r16 = 8,r16 ;; |
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| 266 | st8 [r16] = r2;; |
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| 267 | add r16 = 8,r16 ;; |
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| 268 | st8 [r16] = r3;; |
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| 269 | add r16 = 8,r16 ;; |
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| 270 | st8 [r16] = r4;; |
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| 271 | add r16 = 8,r16 ;; |
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| 272 | st8 [r16] = r5;; |
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| 273 | add r16 = 8,r16 ;; |
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| 274 | st8 [r16] = r6;; |
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| 275 | add r16 = 8,r16 ;; |
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| 276 | st8 [r16] = r7;; |
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| 277 | add r16 = 8,r16 ;; |
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| 278 | st8 [r16] = r8;; |
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| 279 | add r16 = 8,r16 ;; |
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| 280 | st8 [r16] = r9;; |
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| 281 | add r16 = 8,r16 ;; |
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| 282 | st8 [r16] = r10;; |
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| 283 | add r16 = 8,r16 ;; |
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| 284 | st8 [r16] = r11;; |
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| 285 | add r16 = 8,r16 ;; |
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| 286 | st8 [r16] = r12;; |
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| 287 | add r16 = 8,r16 ;; |
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| 288 | st8 [r16] = r13;; |
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| 289 | add r16 = 8,r16 ;; |
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| 290 | st8 [r16] = r14;; |
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| 291 | add r16 = 8,r16 ;; |
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| 292 | st8 [r16] = r15;; |
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| 293 | add r16 = 8,r16 ;; |
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| 294 | |||
| 295 | bsw.1;; |
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| 296 | mov r15 = r16;; |
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| 297 | bsw.0;; |
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| 298 | st8 [r16] = r15;; |
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| 299 | add r16 = 8,r16 ;; |
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| 300 | bsw.1;; |
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| 301 | mov r15 = r17;; |
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| 302 | bsw.0;; |
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| 303 | st8 [r16] = r15;; |
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| 304 | add r16 = 8,r16 ;; |
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| 305 | bsw.1;; |
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| 306 | mov r15 = r18;; |
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| 307 | bsw.0;; |
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| 308 | st8 [r16] = r15;; |
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| 309 | add r16 = 8,r16 ;; |
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| 310 | bsw.1;; |
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| 311 | mov r15 = r19;; |
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| 312 | bsw.0;; |
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| 313 | st8 [r16] = r15;; |
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| 314 | add r16 = 8,r16 ;; |
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| 315 | bsw.1;; |
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| 316 | mov r15 = r20;; |
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| 317 | bsw.0;; |
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| 318 | st8 [r16] = r15;; |
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| 319 | add r16 = 8,r16 ;; |
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| 320 | bsw.1;; |
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| 321 | mov r15 = r21;; |
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| 322 | bsw.0;; |
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| 323 | st8 [r16] = r15;; |
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| 324 | add r16 = 8,r16 ;; |
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| 325 | bsw.1;; |
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| 326 | mov r15 = r22;; |
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| 327 | bsw.0;; |
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| 328 | st8 [r16] = r15;; |
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| 329 | add r16 = 8,r16 ;; |
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| 330 | bsw.1;; |
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| 331 | mov r15 = r23;; |
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| 332 | bsw.0;; |
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| 333 | st8 [r16] = r15;; |
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| 334 | add r16 = 8,r16 ;; |
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| 335 | bsw.1;; |
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| 336 | mov r15 = r24;; |
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| 337 | bsw.0;; |
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| 338 | st8 [r16] = r15;; |
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| 339 | add r16 = 8,r16 ;; |
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| 340 | bsw.1;; |
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| 341 | mov r15 = r25;; |
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| 342 | bsw.0;; |
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| 343 | st8 [r16] = r15;; |
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| 344 | add r16 = 8,r16 ;; |
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| 345 | bsw.1;; |
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| 346 | mov r15 = r26;; |
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| 347 | bsw.0;; |
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| 348 | st8 [r16] = r15;; |
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| 349 | add r16 = 8,r16 ;; |
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| 350 | bsw.1;; |
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| 351 | mov r15 = r27;; |
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| 352 | bsw.0;; |
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| 353 | st8 [r16] = r15;; |
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| 354 | add r16 = 8,r16 ;; |
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| 355 | bsw.1;; |
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| 356 | mov r15 = r28;; |
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| 357 | bsw.0;; |
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| 358 | st8 [r16] = r15;; |
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| 359 | add r16 = 8,r16 ;; |
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| 360 | bsw.1;; |
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| 361 | mov r15 = r29;; |
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| 362 | bsw.0;; |
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| 363 | st8 [r16] = r15;; |
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| 364 | add r16 = 8,r16 ;; |
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| 365 | bsw.1;; |
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| 366 | mov r15 = r30;; |
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| 367 | bsw.0;; |
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| 368 | st8 [r16] = r15;; |
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| 369 | add r16 = 8,r16 ;; |
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| 370 | bsw.1;; |
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| 371 | mov r15 = r31;; |
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| 372 | bsw.0;; |
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| 373 | st8 [r16] = r15;; |
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| 374 | add r16 = 8,r16 ;; |
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| 375 | |||
| 376 | |||
| 377 | st8 [r16] = r32;; |
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| 378 | add r16 = 8,r16 ;; |
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| 379 | st8 [r16] = r33;; |
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| 380 | add r16 = 8,r16 ;; |
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| 381 | st8 [r16] = r34;; |
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| 382 | add r16 = 8,r16 ;; |
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| 383 | st8 [r16] = r35;; |
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| 384 | add r16 = 8,r16 ;; |
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| 385 | st8 [r16] = r36;; |
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| 386 | add r16 = 8,r16 ;; |
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| 387 | st8 [r16] = r37;; |
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| 388 | add r16 = 8,r16 ;; |
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| 389 | st8 [r16] = r38;; |
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| 390 | add r16 = 8,r16 ;; |
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| 391 | st8 [r16] = r39;; |
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| 392 | add r16 = 8,r16 ;; |
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| 393 | st8 [r16] = r40;; |
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| 394 | add r16 = 8,r16 ;; |
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| 395 | st8 [r16] = r41;; |
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| 396 | add r16 = 8,r16 ;; |
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| 397 | st8 [r16] = r42;; |
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| 398 | add r16 = 8,r16 ;; |
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| 399 | st8 [r16] = r43;; |
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| 400 | add r16 = 8,r16 ;; |
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| 401 | st8 [r16] = r44;; |
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| 402 | add r16 = 8,r16 ;; |
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| 403 | st8 [r16] = r45;; |
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| 404 | add r16 = 8,r16 ;; |
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| 405 | st8 [r16] = r46;; |
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| 406 | add r16 = 8,r16 ;; |
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| 407 | st8 [r16] = r47;; |
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| 408 | add r16 = 8,r16 ;; |
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| 409 | st8 [r16] = r48;; |
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| 410 | add r16 = 8,r16 ;; |
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| 411 | st8 [r16] = r49;; |
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| 412 | add r16 = 8,r16 ;; |
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| 413 | st8 [r16] = r50;; |
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| 414 | add r16 = 8,r16 ;; |
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| 415 | st8 [r16] = r51;; |
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| 416 | add r16 = 8,r16 ;; |
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| 417 | st8 [r16] = r52;; |
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| 418 | add r16 = 8,r16 ;; |
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| 419 | st8 [r16] = r53;; |
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| 420 | add r16 = 8,r16 ;; |
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| 421 | st8 [r16] = r54;; |
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| 422 | add r16 = 8,r16 ;; |
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| 423 | st8 [r16] = r55;; |
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| 424 | add r16 = 8,r16 ;; |
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| 425 | st8 [r16] = r56;; |
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| 426 | add r16 = 8,r16 ;; |
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| 427 | st8 [r16] = r57;; |
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| 428 | add r16 = 8,r16 ;; |
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| 429 | st8 [r16] = r58;; |
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| 430 | add r16 = 8,r16 ;; |
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| 431 | st8 [r16] = r59;; |
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| 432 | add r16 = 8,r16 ;; |
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| 433 | st8 [r16] = r60;; |
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| 434 | add r16 = 8,r16 ;; |
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| 435 | st8 [r16] = r61;; |
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| 436 | add r16 = 8,r16 ;; |
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| 437 | st8 [r16] = r62;; |
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| 438 | add r16 = 8,r16 ;; |
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| 439 | st8 [r16] = r63;; |
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| 440 | add r16 = 8,r16 ;; |
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| 441 | |||
| 442 | |||
| 443 | |||
| 444 | st8 [r16] = r64;; |
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| 445 | add r16 = 8,r16 ;; |
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| 446 | st8 [r16] = r65;; |
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| 447 | add r16 = 8,r16 ;; |
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| 448 | st8 [r16] = r66;; |
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| 449 | add r16 = 8,r16 ;; |
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| 450 | st8 [r16] = r67;; |
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| 451 | add r16 = 8,r16 ;; |
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| 452 | st8 [r16] = r68;; |
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| 453 | add r16 = 8,r16 ;; |
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| 454 | st8 [r16] = r69;; |
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| 455 | add r16 = 8,r16 ;; |
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| 456 | st8 [r16] = r70;; |
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| 457 | add r16 = 8,r16 ;; |
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| 458 | st8 [r16] = r71;; |
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| 459 | add r16 = 8,r16 ;; |
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| 460 | st8 [r16] = r72;; |
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| 461 | add r16 = 8,r16 ;; |
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| 462 | st8 [r16] = r73;; |
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| 463 | add r16 = 8,r16 ;; |
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| 464 | st8 [r16] = r74;; |
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| 465 | add r16 = 8,r16 ;; |
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| 466 | st8 [r16] = r75;; |
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| 467 | add r16 = 8,r16 ;; |
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| 468 | st8 [r16] = r76;; |
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| 469 | add r16 = 8,r16 ;; |
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| 470 | st8 [r16] = r77;; |
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| 471 | add r16 = 8,r16 ;; |
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| 472 | st8 [r16] = r78;; |
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| 473 | add r16 = 8,r16 ;; |
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| 474 | st8 [r16] = r79;; |
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| 475 | add r16 = 8,r16 ;; |
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| 476 | st8 [r16] = r80;; |
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| 477 | add r16 = 8,r16 ;; |
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| 478 | st8 [r16] = r81;; |
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| 479 | add r16 = 8,r16 ;; |
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| 480 | st8 [r16] = r82;; |
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| 481 | add r16 = 8,r16 ;; |
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| 482 | st8 [r16] = r83;; |
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| 483 | add r16 = 8,r16 ;; |
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| 484 | st8 [r16] = r84;; |
||
| 485 | add r16 = 8,r16 ;; |
||
| 486 | st8 [r16] = r85;; |
||
| 487 | add r16 = 8,r16 ;; |
||
| 488 | st8 [r16] = r86;; |
||
| 489 | add r16 = 8,r16 ;; |
||
| 490 | st8 [r16] = r87;; |
||
| 491 | add r16 = 8,r16 ;; |
||
| 492 | st8 [r16] = r88;; |
||
| 493 | add r16 = 8,r16 ;; |
||
| 494 | st8 [r16] = r89;; |
||
| 495 | add r16 = 8,r16 ;; |
||
| 496 | st8 [r16] = r90;; |
||
| 497 | add r16 = 8,r16 ;; |
||
| 498 | st8 [r16] = r91;; |
||
| 499 | add r16 = 8,r16 ;; |
||
| 500 | st8 [r16] = r92;; |
||
| 501 | add r16 = 8,r16 ;; |
||
| 502 | st8 [r16] = r93;; |
||
| 503 | add r16 = 8,r16 ;; |
||
| 504 | st8 [r16] = r94;; |
||
| 505 | add r16 = 8,r16 ;; |
||
| 506 | st8 [r16] = r95;; |
||
| 507 | add r16 = 8,r16 ;; |
||
| 508 | |||
| 509 | |||
| 510 | |||
| 511 | st8 [r16] = r96;; |
||
| 512 | add r16 = 8,r16 ;; |
||
| 513 | st8 [r16] = r97;; |
||
| 514 | add r16 = 8,r16 ;; |
||
| 515 | st8 [r16] = r98;; |
||
| 516 | add r16 = 8,r16 ;; |
||
| 517 | st8 [r16] = r99;; |
||
| 518 | add r16 = 8,r16 ;; |
||
| 519 | st8 [r16] = r100;; |
||
| 520 | add r16 = 8,r16 ;; |
||
| 521 | st8 [r16] = r101;; |
||
| 522 | add r16 = 8,r16 ;; |
||
| 523 | st8 [r16] = r102;; |
||
| 524 | add r16 = 8,r16 ;; |
||
| 525 | st8 [r16] = r103;; |
||
| 526 | add r16 = 8,r16 ;; |
||
| 527 | st8 [r16] = r104;; |
||
| 528 | add r16 = 8,r16 ;; |
||
| 529 | st8 [r16] = r105;; |
||
| 530 | add r16 = 8,r16 ;; |
||
| 531 | st8 [r16] = r106;; |
||
| 532 | add r16 = 8,r16 ;; |
||
| 533 | st8 [r16] = r107;; |
||
| 534 | add r16 = 8,r16 ;; |
||
| 535 | st8 [r16] = r108;; |
||
| 536 | add r16 = 8,r16 ;; |
||
| 537 | st8 [r16] = r109;; |
||
| 538 | add r16 = 8,r16 ;; |
||
| 539 | st8 [r16] = r110;; |
||
| 540 | add r16 = 8,r16 ;; |
||
| 541 | st8 [r16] = r111;; |
||
| 542 | add r16 = 8,r16 ;; |
||
| 543 | st8 [r16] = r112;; |
||
| 544 | add r16 = 8,r16 ;; |
||
| 545 | st8 [r16] = r113;; |
||
| 546 | add r16 = 8,r16 ;; |
||
| 547 | st8 [r16] = r114;; |
||
| 548 | add r16 = 8,r16 ;; |
||
| 549 | st8 [r16] = r115;; |
||
| 550 | add r16 = 8,r16 ;; |
||
| 551 | st8 [r16] = r116;; |
||
| 552 | add r16 = 8,r16 ;; |
||
| 553 | st8 [r16] = r117;; |
||
| 554 | add r16 = 8,r16 ;; |
||
| 555 | st8 [r16] = r118;; |
||
| 556 | add r16 = 8,r16 ;; |
||
| 557 | st8 [r16] = r119;; |
||
| 558 | add r16 = 8,r16 ;; |
||
| 559 | st8 [r16] = r120;; |
||
| 560 | add r16 = 8,r16 ;; |
||
| 561 | st8 [r16] = r121;; |
||
| 562 | add r16 = 8,r16 ;; |
||
| 563 | st8 [r16] = r122;; |
||
| 564 | add r16 = 8,r16 ;; |
||
| 565 | st8 [r16] = r123;; |
||
| 566 | add r16 = 8,r16 ;; |
||
| 567 | st8 [r16] = r124;; |
||
| 568 | add r16 = 8,r16 ;; |
||
| 569 | st8 [r16] = r125;; |
||
| 570 | add r16 = 8,r16 ;; |
||
| 571 | st8 [r16] = r126;; |
||
| 572 | add r16 = 8,r16 ;; |
||
| 573 | st8 [r16] = r127;; |
||
| 574 | add r16 = 8,r16 ;; |
||
| 575 | |||
| 576 | |||
| 577 | |||
| 578 | br.ret.sptk.many b0;; |
||
| 579 | |||
| 580 | |||
| 581 | |||
| 582 | |||
| 583 | |||
| 212 | vana | 584 | .macro Handler o h |
| 585 | .org IVT + \o |
||
| 586 | br \h;; |
||
| 587 | .endm |
||
| 588 | |||
| 220 | vana | 589 | .macro Handler2 o |
| 590 | .org IVT + \o |
||
| 238 | vana | 591 | br.call.sptk.many b0 = dump_gregs;; |
| 592 | mov r16 = \o ;; |
||
| 593 | bsw.1;; |
||
| 220 | vana | 594 | br universal_handler;; |
| 595 | .endm |
||
| 212 | vana | 596 | |
| 597 | |||
| 220 | vana | 598 | |
| 212 | vana | 599 | .global IVT |
| 600 | .align 32768 |
||
| 601 | IVT: |
||
| 602 | |||
| 220 | vana | 603 | |
| 604 | Handler2 0x0000 |
||
| 605 | Handler2 0x0400 |
||
| 606 | Handler2 0x0800 |
||
| 607 | Handler2 0x0c00 |
||
| 608 | Handler2 0x1000 |
||
| 609 | Handler2 0x1400 |
||
| 610 | Handler2 0x1800 |
||
| 611 | Handler2 0x1c00 |
||
| 612 | Handler2 0x2000 |
||
| 613 | Handler2 0x2400 |
||
| 614 | Handler2 0x2800 |
||
| 212 | vana | 615 | Handler 0x2c00 break_instruction |
| 435 | jermar | 616 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
| 220 | vana | 617 | Handler2 0x3400 |
| 618 | Handler2 0x3800 |
||
| 619 | Handler2 0x3c00 |
||
| 620 | Handler2 0x4000 |
||
| 621 | Handler2 0x4400 |
||
| 622 | Handler2 0x4800 |
||
| 623 | Handler2 0x4c00 |
||
| 624 | |||
| 625 | Handler2 0x5000 |
||
| 626 | Handler2 0x5100 |
||
| 627 | Handler2 0x5200 |
||
| 628 | Handler2 0x5300 |
||
| 238 | vana | 629 | #Handler 0x5400 general_exception |
| 630 | Handler2 0x5400 |
||
| 220 | vana | 631 | Handler2 0x5500 |
| 632 | Handler2 0x5600 |
||
| 633 | Handler2 0x5700 |
||
| 634 | Handler2 0x5800 |
||
| 635 | Handler2 0x5900 |
||
| 636 | Handler2 0x5a00 |
||
| 637 | Handler2 0x5b00 |
||
| 638 | Handler2 0x5c00 |
||
| 639 | Handler2 0x5d00 |
||
| 640 | Handler2 0x5e00 |
||
| 641 | Handler2 0x5f00 |
||
| 212 | vana | 642 | |
| 220 | vana | 643 | Handler2 0x6000 |
| 644 | Handler2 0x6100 |
||
| 645 | Handler2 0x6200 |
||
| 646 | Handler2 0x6300 |
||
| 647 | Handler2 0x6400 |
||
| 648 | Handler2 0x6500 |
||
| 649 | Handler2 0x6600 |
||
| 650 | Handler2 0x6700 |
||
| 651 | Handler2 0x6800 |
||
| 652 | Handler2 0x6900 |
||
| 653 | Handler2 0x6a00 |
||
| 654 | Handler2 0x6b00 |
||
| 655 | Handler2 0x6c00 |
||
| 656 | Handler2 0x6d00 |
||
| 657 | Handler2 0x6e00 |
||
| 658 | Handler2 0x6f00 |
||
| 212 | vana | 659 | |
| 220 | vana | 660 | Handler2 0x7000 |
| 661 | Handler2 0x7100 |
||
| 662 | Handler2 0x7200 |
||
| 663 | Handler2 0x7300 |
||
| 664 | Handler2 0x7400 |
||
| 665 | Handler2 0x7500 |
||
| 666 | Handler2 0x7600 |
||
| 667 | Handler2 0x7700 |
||
| 668 | Handler2 0x7800 |
||
| 669 | Handler2 0x7900 |
||
| 670 | Handler2 0x7a00 |
||
| 671 | Handler2 0x7b00 |
||
| 672 | Handler2 0x7c00 |
||
| 673 | Handler2 0x7d00 |
||
| 674 | Handler2 0x7e00 |
||
| 675 | Handler2 0x7f00 |
||
| 212 | vana | 676 | |
| 677 | |||
| 220 | vana | 678 | |
| 679 | |||
| 680 | |||
| 681 | |||
| 682 | |||
| 683 | |||
| 212 | vana | 684 | .align 32768 |
| 238 | vana | 685 | .global REG_DUMP |
| 686 | |||
| 687 | REG_DUMP: |
||
| 688 | .space 128*8 |
||
| 689 |