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212 vana 1
#
2
# Copyright (C) 2005 Jakub Vana
3
# All rights reserved.
4
#
5
# Redistribution and use in source and binary forms, with or without
6
# modification, are permitted provided that the following conditions
7
# are met:
8
#
9
# - Redistributions of source code must retain the above copyright
10
#   notice, this list of conditions and the following disclaimer.
11
# - Redistributions in binary form must reproduce the above copyright
12
#   notice, this list of conditions and the following disclaimer in the
13
#   documentation and/or other materials provided with the distribution.
14
# - The name of the author may not be used to endorse or promote products
15
#   derived from this software without specific prior written permission.
16
#
17
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
#
28
 
29
 
438 jermar 30
/** Heavyweight interrupt handler
31
 *
435 jermar 32
 * This macro roughly follows steps from 1 to 19 described in
33
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
34
 *
438 jermar 35
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
36
 * This goal is achieved by using procedure calls after RSE becomes operational.
37
 *
435 jermar 38
 * Some steps are skipped (enabling and disabling interrupts).
39
 * Some steps are not fully supported yet (e.g. interruptions
438 jermar 40
 * from userspace and floating-point context).
435 jermar 41
 */
42
.macro HEAVYWEIGHT_HANDLER offs handler
43
    .org IVT + \offs
212 vana 44
 
435 jermar 45
    /* 1. copy interrupt registers into bank 0 */
46
	mov r24 = cr.iip
47
	mov r25 = cr.ipsr
48
	mov r26 = cr.iipa
49
	mov r27 = cr.isr
50
	mov r28 = cr.ifa
51
 
52
    /* 2. preserve predicate register into bank 0 */
53
	mov r29 = pr ;;
54
 
438 jermar 55
    /* 3. switch to kernel memory stack */
435 jermar 56
	/* TODO: support interruptions from userspace */
57
	/* assume kernel stack */
58
 
439 jermar 59
    /* 4. save registers in bank 0 into memory stack */
441 jermar 60
	add r12 = -8, r12 ;;
61
 
435 jermar 62
	st8 [r12] = r29, -8 ;;	/* save predicate registers */
438 jermar 63
 
64
	st8 [r12] = r24, -8 ;;	/* save cr.iip */
65
	st8 [r12] = r25, -8 ;;	/* save cr.ipsr */
66
	st8 [r12] = r26, -8 ;;	/* save cr.iipa */
435 jermar 67
	st8 [r12] = r27, -8 ;;	/* save cr.isr */
438 jermar 68
	st8 [r12] = r28, -8 ;;	/* save cr.ifa */		
69
 
70
    /* 5. RSE switch from interrupted context */
435 jermar 71
    	.auto
72
	mov r24 = ar.rsc
73
	mov r25 = ar.pfs
74
	cover
75
	mov r26 = cr.ifs
76
 
77
	st8 [r12] = r24, -8	/* save ar.rsc */
78
	st8 [r12] = r25, -8	/* save ar.pfs */
79
	st8 [r12] = r26, -8	/* save ar.ifs */
80
 
81
	and r30 = ~3, r24
82
	mov ar.rsc = r30	/* place RSE in enforced lazy mode */
83
 
84
	mov r27 = ar.rnat
85
	mov r28 = ar.bspstore
86
 
87
	/* assume kernel backing store */
88
	mov ar.bspstore = r28
89
 
90
	mov r29 = ar.bsp
91
 
92
	st8 [r12] = r27, -8	/* save ar.rnat */
93
	st8 [r12] = r28, -8	/* save ar.bspstore */
442 vana 94
	st8 [r12] = r29		/* save ar.bsp */
435 jermar 95
 
96
	mov ar.rsc = r24	/* restore RSE's setting */
97
	.explicit
98
 
438 jermar 99
    /* the rest of the save-handler can be kept outside IVT */
100
 
101
	movl r24 = \handler
102
	mov r25 = b0
103
	br.call.sptk.many rp = heavyweight_handler_inner
104
0:	mov b0 = r25	
105
 
439 jermar 106
	br heavyweight_handler_finalize
438 jermar 107
.endm
108
 
109
.global heavyweight_handler_inner
110
heavyweight_handler_inner:
111
	/*
112
	 * From this point, the rest of the interrupted context
113
	 * will be preserved in stacked registers and backing store.
114
	 */
115
	alloc loc0 = ar.pfs, 0, 46, 0, 0 ;;
116
 
117
	/* copy handler address (r24 from bank 0 will be invisible soon) */
118
	mov loc1 = r24
119
 
435 jermar 120
    /* 6. switch to bank 1 and reenable PSR.ic */
121
	ssm 0x2000
122
	bsw.1 ;;
123
	srlz.d
124
 
125
    /* 7. preserve branch and application registers */
438 jermar 126
    	mov loc2 = ar.unat
127
	mov loc3 = ar.lc
128
	mov loc4 = ar.ec
129
	mov loc5 = ar.ccv
130
	mov loc6 = ar.csd
131
	mov loc7 = ar.ssd
435 jermar 132
 
438 jermar 133
	mov loc8 = b0
134
	mov loc9 = b1
135
	mov loc10 = b2
136
	mov loc11 = b3
137
	mov loc12 = b4
138
	mov loc13 = b5
139
	mov loc14 = b6
140
	mov loc15 = b7
141
 
435 jermar 142
    /* 8. preserve general and floating-point registers */
143
	/* TODO: save floating-point context */
438 jermar 144
	mov loc16 = r1
145
	mov loc17 = r2
146
	mov loc18 = r3
147
	mov loc19 = r4
148
	mov loc20 = r5
149
	mov loc21 = r6
150
	mov loc22 = r7
151
	mov loc23 = r8
152
	mov loc24 = r9
153
	mov loc25 = r10
154
	mov loc26 = r11
155
	/* skip r12 (stack pointer) */
156
	mov loc27 = r13
157
	mov loc28 = r14
158
	mov loc29 = r15
159
	mov loc30 = r16
160
	mov loc31 = r17
161
	mov loc32 = r18
162
	mov loc33 = r19
163
	mov loc34 = r20
164
	mov loc35 = r21
165
	mov loc36 = r22
166
	mov loc37 = r23
167
	mov loc38 = r24
168
	mov loc39 = r25
169
	mov loc40 = r26
170
	mov loc41 = r27
171
	mov loc42 = r28
172
	mov loc43 = r29
173
	mov loc44 = r30
174
	mov loc45 = r31
175
 
435 jermar 176
    /* 9. skipped (will not enable interrupts) */
238 vana 177
 
438 jermar 178
    /* 10. call handler */
179
    	mov b1 = loc1
180
	br.call.sptk.many b0 = b1
181
 
182
    /* 11. return from handler */
183
0:
184
 
435 jermar 185
    /* 12. skipped (will not disable interrupts) */
438 jermar 186
 
435 jermar 187
    /* 13. restore general and floating-point registers */
188
	/* TODO: restore floating-point context */
438 jermar 189
	mov r1 = loc16
190
	mov r2 = loc17
191
	mov r3 = loc18
192
	mov r4 = loc19
193
	mov r5 = loc20
194
	mov r6 = loc21
195
	mov r7 = loc22
196
	mov r8 = loc23
197
	mov r9 = loc24
198
	mov r10 = loc25
199
	mov r11 = loc26
200
	/* skip r12 (stack pointer) */
201
	mov r13 = loc27
202
	mov r14 = loc28
203
	mov r15 = loc29
204
	mov r16 = loc30
205
	mov r17 = loc31
206
	mov r18 = loc32
207
	mov r19 = loc33
208
	mov r20 = loc34
209
	mov r21 = loc35
210
	mov r22 = loc36
211
	mov r23 = loc37
212
	mov r24 = loc38
213
	mov r25 = loc39
214
	mov r26 = loc40
215
	mov r27 = loc41
216
	mov r28 = loc42
217
	mov r29 = loc43
218
	mov r30 = loc44
219
	mov r31 = loc45
435 jermar 220
 
221
    /* 14. restore branch and application registers */
438 jermar 222
    	mov ar.unat = loc2
223
	mov ar.lc = loc3
224
	mov ar.ec = loc4
225
	mov ar.ccv = loc5
226
	mov ar.csd = loc6
227
	mov ar.ssd = loc7
435 jermar 228
 
438 jermar 229
	mov b0 = loc8
230
	mov b1 = loc9
231
	mov b2 = loc10
232
	mov b3 = loc11
233
	mov b4 = loc12
234
	mov b5 = loc13
235
	mov b6 = loc14
236
	mov b7 = loc15
237
 
435 jermar 238
    /* 15. disable PSR.ic and switch to bank 0 */
239
	rsm 0x2000
240
	bsw.0 ;;
241
	srlz.d
438 jermar 242
 
243
	mov ar.pfs = loc0
244
	br.ret.sptk.many rp
245
 
246
.global heavyweight_handler_finalize
247
heavyweight_handler_finalize:
248
    /* 16. RSE switch to interrupted context */
435 jermar 249
 
250
    /* 17. restore interruption state from memory stack */
251
 
252
    /* 18. restore predicate registers from memory stack */
253
 
254
    /* 19. return from interruption */
255
	rfi
256
 
257
 
438 jermar 258
 
259
 
238 vana 260
dump_gregs:
261
mov r16 = REG_DUMP;;
262
st8 [r16] = r0;;
263
add r16 = 8,r16 ;;
264
st8 [r16] = r1;;
265
add r16 = 8,r16 ;;
266
st8 [r16] = r2;;
267
add r16 = 8,r16 ;;
268
st8 [r16] = r3;;
269
add r16 = 8,r16 ;;
270
st8 [r16] = r4;;
271
add r16 = 8,r16 ;;
272
st8 [r16] = r5;;
273
add r16 = 8,r16 ;;
274
st8 [r16] = r6;;
275
add r16 = 8,r16 ;;
276
st8 [r16] = r7;;
277
add r16 = 8,r16 ;;
278
st8 [r16] = r8;;
279
add r16 = 8,r16 ;;
280
st8 [r16] = r9;;
281
add r16 = 8,r16 ;;
282
st8 [r16] = r10;;
283
add r16 = 8,r16 ;;
284
st8 [r16] = r11;;
285
add r16 = 8,r16 ;;
286
st8 [r16] = r12;;
287
add r16 = 8,r16 ;;
288
st8 [r16] = r13;;
289
add r16 = 8,r16 ;;
290
st8 [r16] = r14;;
291
add r16 = 8,r16 ;;
292
st8 [r16] = r15;;
293
add r16 = 8,r16 ;;
294
 
295
bsw.1;;
296
mov r15 = r16;;
297
bsw.0;;
298
st8 [r16] = r15;;
299
add r16 = 8,r16 ;;
300
bsw.1;;
301
mov r15 = r17;;
302
bsw.0;;
303
st8 [r16] = r15;;
304
add r16 = 8,r16 ;;
305
bsw.1;;
306
mov r15 = r18;;
307
bsw.0;;
308
st8 [r16] = r15;;
309
add r16 = 8,r16 ;;
310
bsw.1;;
311
mov r15 = r19;;
312
bsw.0;;
313
st8 [r16] = r15;;
314
add r16 = 8,r16 ;;
315
bsw.1;;
316
mov r15 = r20;;
317
bsw.0;;
318
st8 [r16] = r15;;
319
add r16 = 8,r16 ;;
320
bsw.1;;
321
mov r15 = r21;;
322
bsw.0;;
323
st8 [r16] = r15;;
324
add r16 = 8,r16 ;;
325
bsw.1;;
326
mov r15 = r22;;
327
bsw.0;;
328
st8 [r16] = r15;;
329
add r16 = 8,r16 ;;
330
bsw.1;;
331
mov r15 = r23;;
332
bsw.0;;
333
st8 [r16] = r15;;
334
add r16 = 8,r16 ;;
335
bsw.1;;
336
mov r15 = r24;;
337
bsw.0;;
338
st8 [r16] = r15;;
339
add r16 = 8,r16 ;;
340
bsw.1;;
341
mov r15 = r25;;
342
bsw.0;;
343
st8 [r16] = r15;;
344
add r16 = 8,r16 ;;
345
bsw.1;;
346
mov r15 = r26;;
347
bsw.0;;
348
st8 [r16] = r15;;
349
add r16 = 8,r16 ;;
350
bsw.1;;
351
mov r15 = r27;;
352
bsw.0;;
353
st8 [r16] = r15;;
354
add r16 = 8,r16 ;;
355
bsw.1;;
356
mov r15 = r28;;
357
bsw.0;;
358
st8 [r16] = r15;;
359
add r16 = 8,r16 ;;
360
bsw.1;;
361
mov r15 = r29;;
362
bsw.0;;
363
st8 [r16] = r15;;
364
add r16 = 8,r16 ;;
365
bsw.1;;
366
mov r15 = r30;;
367
bsw.0;;
368
st8 [r16] = r15;;
369
add r16 = 8,r16 ;;
370
bsw.1;;
371
mov r15 = r31;;
372
bsw.0;;
373
st8 [r16] = r15;;
374
add r16 = 8,r16 ;;
375
 
376
 
377
st8 [r16] = r32;;
378
add r16 = 8,r16 ;;
379
st8 [r16] = r33;;
380
add r16 = 8,r16 ;;
381
st8 [r16] = r34;;
382
add r16 = 8,r16 ;;
383
st8 [r16] = r35;;
384
add r16 = 8,r16 ;;
385
st8 [r16] = r36;;
386
add r16 = 8,r16 ;;
387
st8 [r16] = r37;;
388
add r16 = 8,r16 ;;
389
st8 [r16] = r38;;
390
add r16 = 8,r16 ;;
391
st8 [r16] = r39;;
392
add r16 = 8,r16 ;;
393
st8 [r16] = r40;;
394
add r16 = 8,r16 ;;
395
st8 [r16] = r41;;
396
add r16 = 8,r16 ;;
397
st8 [r16] = r42;;
398
add r16 = 8,r16 ;;
399
st8 [r16] = r43;;
400
add r16 = 8,r16 ;;
401
st8 [r16] = r44;;
402
add r16 = 8,r16 ;;
403
st8 [r16] = r45;;
404
add r16 = 8,r16 ;;
405
st8 [r16] = r46;;
406
add r16 = 8,r16 ;;
407
st8 [r16] = r47;;
408
add r16 = 8,r16 ;;
409
st8 [r16] = r48;;
410
add r16 = 8,r16 ;;
411
st8 [r16] = r49;;
412
add r16 = 8,r16 ;;
413
st8 [r16] = r50;;
414
add r16 = 8,r16 ;;
415
st8 [r16] = r51;;
416
add r16 = 8,r16 ;;
417
st8 [r16] = r52;;
418
add r16 = 8,r16 ;;
419
st8 [r16] = r53;;
420
add r16 = 8,r16 ;;
421
st8 [r16] = r54;;
422
add r16 = 8,r16 ;;
423
st8 [r16] = r55;;
424
add r16 = 8,r16 ;;
425
st8 [r16] = r56;;
426
add r16 = 8,r16 ;;
427
st8 [r16] = r57;;
428
add r16 = 8,r16 ;;
429
st8 [r16] = r58;;
430
add r16 = 8,r16 ;;
431
st8 [r16] = r59;;
432
add r16 = 8,r16 ;;
433
st8 [r16] = r60;;
434
add r16 = 8,r16 ;;
435
st8 [r16] = r61;;
436
add r16 = 8,r16 ;;
437
st8 [r16] = r62;;
438
add r16 = 8,r16 ;;
439
st8 [r16] = r63;;
440
add r16 = 8,r16 ;;
441
 
442
 
443
 
444
st8 [r16] = r64;;
445
add r16 = 8,r16 ;;
446
st8 [r16] = r65;;
447
add r16 = 8,r16 ;;
448
st8 [r16] = r66;;
449
add r16 = 8,r16 ;;
450
st8 [r16] = r67;;
451
add r16 = 8,r16 ;;
452
st8 [r16] = r68;;
453
add r16 = 8,r16 ;;
454
st8 [r16] = r69;;
455
add r16 = 8,r16 ;;
456
st8 [r16] = r70;;
457
add r16 = 8,r16 ;;
458
st8 [r16] = r71;;
459
add r16 = 8,r16 ;;
460
st8 [r16] = r72;;
461
add r16 = 8,r16 ;;
462
st8 [r16] = r73;;
463
add r16 = 8,r16 ;;
464
st8 [r16] = r74;;
465
add r16 = 8,r16 ;;
466
st8 [r16] = r75;;
467
add r16 = 8,r16 ;;
468
st8 [r16] = r76;;
469
add r16 = 8,r16 ;;
470
st8 [r16] = r77;;
471
add r16 = 8,r16 ;;
472
st8 [r16] = r78;;
473
add r16 = 8,r16 ;;
474
st8 [r16] = r79;;
475
add r16 = 8,r16 ;;
476
st8 [r16] = r80;;
477
add r16 = 8,r16 ;;
478
st8 [r16] = r81;;
479
add r16 = 8,r16 ;;
480
st8 [r16] = r82;;
481
add r16 = 8,r16 ;;
482
st8 [r16] = r83;;
483
add r16 = 8,r16 ;;
484
st8 [r16] = r84;;
485
add r16 = 8,r16 ;;
486
st8 [r16] = r85;;
487
add r16 = 8,r16 ;;
488
st8 [r16] = r86;;
489
add r16 = 8,r16 ;;
490
st8 [r16] = r87;;
491
add r16 = 8,r16 ;;
492
st8 [r16] = r88;;
493
add r16 = 8,r16 ;;
494
st8 [r16] = r89;;
495
add r16 = 8,r16 ;;
496
st8 [r16] = r90;;
497
add r16 = 8,r16 ;;
498
st8 [r16] = r91;;
499
add r16 = 8,r16 ;;
500
st8 [r16] = r92;;
501
add r16 = 8,r16 ;;
502
st8 [r16] = r93;;
503
add r16 = 8,r16 ;;
504
st8 [r16] = r94;;
505
add r16 = 8,r16 ;;
506
st8 [r16] = r95;;
507
add r16 = 8,r16 ;;
508
 
509
 
510
 
511
st8 [r16] = r96;;
512
add r16 = 8,r16 ;;
513
st8 [r16] = r97;;
514
add r16 = 8,r16 ;;
515
st8 [r16] = r98;;
516
add r16 = 8,r16 ;;
517
st8 [r16] = r99;;
518
add r16 = 8,r16 ;;
519
st8 [r16] = r100;;
520
add r16 = 8,r16 ;;
521
st8 [r16] = r101;;
522
add r16 = 8,r16 ;;
523
st8 [r16] = r102;;
524
add r16 = 8,r16 ;;
525
st8 [r16] = r103;;
526
add r16 = 8,r16 ;;
527
st8 [r16] = r104;;
528
add r16 = 8,r16 ;;
529
st8 [r16] = r105;;
530
add r16 = 8,r16 ;;
531
st8 [r16] = r106;;
532
add r16 = 8,r16 ;;
533
st8 [r16] = r107;;
534
add r16 = 8,r16 ;;
535
st8 [r16] = r108;;
536
add r16 = 8,r16 ;;
537
st8 [r16] = r109;;
538
add r16 = 8,r16 ;;
539
st8 [r16] = r110;;
540
add r16 = 8,r16 ;;
541
st8 [r16] = r111;;
542
add r16 = 8,r16 ;;
543
st8 [r16] = r112;;
544
add r16 = 8,r16 ;;
545
st8 [r16] = r113;;
546
add r16 = 8,r16 ;;
547
st8 [r16] = r114;;
548
add r16 = 8,r16 ;;
549
st8 [r16] = r115;;
550
add r16 = 8,r16 ;;
551
st8 [r16] = r116;;
552
add r16 = 8,r16 ;;
553
st8 [r16] = r117;;
554
add r16 = 8,r16 ;;
555
st8 [r16] = r118;;
556
add r16 = 8,r16 ;;
557
st8 [r16] = r119;;
558
add r16 = 8,r16 ;;
559
st8 [r16] = r120;;
560
add r16 = 8,r16 ;;
561
st8 [r16] = r121;;
562
add r16 = 8,r16 ;;
563
st8 [r16] = r122;;
564
add r16 = 8,r16 ;;
565
st8 [r16] = r123;;
566
add r16 = 8,r16 ;;
567
st8 [r16] = r124;;
568
add r16 = 8,r16 ;;
569
st8 [r16] = r125;;
570
add r16 = 8,r16 ;;
571
st8 [r16] = r126;;
572
add r16 = 8,r16 ;;
573
st8 [r16] = r127;;
574
add r16 = 8,r16 ;;
575
 
576
 
577
 
578
br.ret.sptk.many b0;;
579
 
580
 
581
 
582
 
583
 
212 vana 584
.macro Handler o h
585
.org IVT + \o
586
br \h;;
587
.endm
588
 
220 vana 589
.macro Handler2 o 
590
.org IVT + \o
238 vana 591
br.call.sptk.many b0 = dump_gregs;;
592
mov r16 = \o ;;
593
bsw.1;;
220 vana 594
br universal_handler;;
595
.endm
212 vana 596
 
597
 
220 vana 598
 
212 vana 599
.global IVT
600
.align 32768
601
IVT:
602
 
220 vana 603
 
604
Handler2 0x0000
605
Handler2 0x0400
606
Handler2 0x0800
607
Handler2 0x0c00
608
Handler2 0x1000
609
Handler2 0x1400
610
Handler2 0x1800
611
Handler2 0x1c00
612
Handler2 0x2000
613
Handler2 0x2400
614
Handler2 0x2800
212 vana 615
Handler 0x2c00 break_instruction
435 jermar 616
HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
220 vana 617
Handler2 0x3400
618
Handler2 0x3800
619
Handler2 0x3c00
620
Handler2 0x4000
621
Handler2 0x4400
622
Handler2 0x4800
623
Handler2 0x4c00
624
 
625
Handler2 0x5000
626
Handler2 0x5100
627
Handler2 0x5200
628
Handler2 0x5300
238 vana 629
#Handler 0x5400 general_exception
630
Handler2 0x5400
220 vana 631
Handler2 0x5500
632
Handler2 0x5600
633
Handler2 0x5700
634
Handler2 0x5800
635
Handler2 0x5900
636
Handler2 0x5a00
637
Handler2 0x5b00
638
Handler2 0x5c00
639
Handler2 0x5d00
640
Handler2 0x5e00
641
Handler2 0x5f00
212 vana 642
 
220 vana 643
Handler2 0x6000
644
Handler2 0x6100
645
Handler2 0x6200
646
Handler2 0x6300
647
Handler2 0x6400
648
Handler2 0x6500
649
Handler2 0x6600
650
Handler2 0x6700
651
Handler2 0x6800
652
Handler2 0x6900
653
Handler2 0x6a00
654
Handler2 0x6b00
655
Handler2 0x6c00
656
Handler2 0x6d00
657
Handler2 0x6e00
658
Handler2 0x6f00
212 vana 659
 
220 vana 660
Handler2 0x7000
661
Handler2 0x7100
662
Handler2 0x7200
663
Handler2 0x7300
664
Handler2 0x7400
665
Handler2 0x7500
666
Handler2 0x7600
667
Handler2 0x7700
668
Handler2 0x7800
669
Handler2 0x7900
670
Handler2 0x7a00
671
Handler2 0x7b00
672
Handler2 0x7c00
673
Handler2 0x7d00
674
Handler2 0x7e00
675
Handler2 0x7f00
212 vana 676
 
677
 
220 vana 678
 
679
 
680
 
681
 
682
 
683
 
212 vana 684
.align 32768
238 vana 685
.global REG_DUMP
686
 
687
REG_DUMP:
688
.space 128*8
689