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1 | jermar | 1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #include <arch/types.h> |
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11 | jermar | 30 | #include <arch/smp/apic.h> |
31 | #include <arch/smp/ap.h> |
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34 | jermar | 32 | #include <arch/smp/mps.h> |
693 | decky | 33 | #include <arch/boot/boot.h> |
1 | jermar | 34 | #include <mm/page.h> |
35 | #include <time/delay.h> |
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576 | palkovsky | 36 | #include <interrupt.h> |
1 | jermar | 37 | #include <arch/interrupt.h> |
38 | #include <print.h> |
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39 | #include <arch/asm.h> |
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40 | #include <arch.h> |
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41 | |||
458 | decky | 42 | #ifdef CONFIG_SMP |
16 | jermar | 43 | |
1 | jermar | 44 | /* |
512 | jermar | 45 | * Advanced Programmable Interrupt Controller for SMP systems. |
1 | jermar | 46 | * Tested on: |
750 | jermar | 47 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
523 | jermar | 48 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
516 | jermar | 49 | * VMware Workstation 5.5 with 2 CPUs |
1 | jermar | 50 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
437 | decky | 51 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
52 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
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1 | jermar | 53 | */ |
54 | |||
55 | /* |
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56 | * These variables either stay configured as initilalized, or are changed by |
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57 | * the MP configuration code. |
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58 | * |
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59 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
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60 | * optimize the code too much and accesses to l_apic and io_apic, that must |
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61 | * always be 32-bit, would use byte oriented instructions. |
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62 | */ |
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63 | volatile __u32 *l_apic = (__u32 *) 0xfee00000; |
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64 | volatile __u32 *io_apic = (__u32 *) 0xfec00000; |
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65 | |||
66 | __u32 apic_id_mask = 0; |
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67 | |||
514 | jermar | 68 | static int apic_poll_errors(void); |
1 | jermar | 69 | |
515 | jermar | 70 | #ifdef LAPIC_VERBOSE |
514 | jermar | 71 | static char *delmod_str[] = { |
72 | "Fixed", |
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73 | "Lowest Priority", |
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74 | "SMI", |
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75 | "Reserved", |
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76 | "NMI", |
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77 | "INIT", |
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78 | "STARTUP", |
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79 | "ExtInt" |
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80 | }; |
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81 | |||
82 | static char *destmod_str[] = { |
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83 | "Physical", |
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84 | "Logical" |
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85 | }; |
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86 | |||
87 | static char *trigmod_str[] = { |
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88 | "Edge", |
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89 | "Level" |
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90 | }; |
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91 | |||
92 | static char *mask_str[] = { |
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93 | "Unmasked", |
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94 | "Masked" |
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95 | }; |
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96 | |||
97 | static char *delivs_str[] = { |
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98 | "Idle", |
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99 | "Send Pending" |
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100 | }; |
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101 | |||
102 | static char *tm_mode_str[] = { |
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103 | "One-shot", |
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104 | "Periodic" |
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105 | }; |
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106 | |||
107 | static char *intpol_str[] = { |
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108 | "Polarity High", |
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109 | "Polarity Low" |
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110 | }; |
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515 | jermar | 111 | #endif /* LAPIC_VERBOSE */ |
514 | jermar | 112 | |
576 | palkovsky | 113 | |
114 | static void apic_spurious(int n, void *stack); |
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115 | static void l_apic_timer_interrupt(int n, void *stack); |
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116 | |||
513 | jermar | 117 | /** Initialize APIC on BSP. */ |
1 | jermar | 118 | void apic_init(void) |
119 | { |
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515 | jermar | 120 | io_apic_id_t idreg; |
121 | int i; |
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1 | jermar | 122 | |
576 | palkovsky | 123 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious); |
1 | jermar | 124 | |
125 | enable_irqs_function = io_apic_enable_irqs; |
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126 | disable_irqs_function = io_apic_disable_irqs; |
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127 | eoi_function = l_apic_eoi; |
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128 | |||
129 | /* |
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130 | * Configure interrupt routing. |
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131 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
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132 | * Other interrupts will be forwarded to the lowest priority CPU. |
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133 | */ |
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134 | io_apic_disable_irqs(0xffff); |
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576 | palkovsky | 135 | exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt); |
515 | jermar | 136 | for (i = 0; i < IRQ_COUNT; i++) { |
1 | jermar | 137 | int pin; |
138 | |||
512 | jermar | 139 | if ((pin = smp_irq_to_pin(i)) != -1) { |
515 | jermar | 140 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI); |
512 | jermar | 141 | } |
1 | jermar | 142 | } |
143 | |||
144 | /* |
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145 | * Ensure that io_apic has unique ID. |
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146 | */ |
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515 | jermar | 147 | idreg.value = io_apic_read(IOAPICID); |
148 | if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
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149 | for (i = 0; i < APIC_ID_COUNT; i++) { |
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1 | jermar | 150 | if (!((1<<i) & apic_id_mask)) { |
515 | jermar | 151 | idreg.apic_id = i; |
152 | io_apic_write(IOAPICID, idreg.value); |
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1 | jermar | 153 | break; |
154 | } |
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155 | } |
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156 | } |
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157 | |||
158 | /* |
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159 | * Configure the BSP's lapic. |
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160 | */ |
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161 | l_apic_init(); |
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515 | jermar | 162 | |
1 | jermar | 163 | l_apic_debug(); |
164 | } |
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165 | |||
514 | jermar | 166 | /** APIC spurious interrupt handler. |
167 | * |
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168 | * @param n Interrupt vector. |
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169 | * @param stack Interrupted stack. |
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170 | */ |
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576 | palkovsky | 171 | void apic_spurious(int n, void *stack) |
1 | jermar | 172 | { |
15 | jermar | 173 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
1 | jermar | 174 | } |
175 | |||
514 | jermar | 176 | /** Poll for APIC errors. |
177 | * |
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178 | * Examine Error Status Register and report all errors found. |
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179 | * |
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180 | * @return 0 on error, 1 on success. |
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181 | */ |
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1 | jermar | 182 | int apic_poll_errors(void) |
183 | { |
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514 | jermar | 184 | esr_t esr; |
1 | jermar | 185 | |
514 | jermar | 186 | esr.value = l_apic[ESR]; |
1 | jermar | 187 | |
514 | jermar | 188 | if (esr.send_checksum_error) |
515 | jermar | 189 | printf("Send Checksum Error\n"); |
514 | jermar | 190 | if (esr.receive_checksum_error) |
515 | jermar | 191 | printf("Receive Checksum Error\n"); |
514 | jermar | 192 | if (esr.send_accept_error) |
1 | jermar | 193 | printf("Send Accept Error\n"); |
514 | jermar | 194 | if (esr.receive_accept_error) |
1 | jermar | 195 | printf("Receive Accept Error\n"); |
514 | jermar | 196 | if (esr.send_illegal_vector) |
1 | jermar | 197 | printf("Send Illegal Vector\n"); |
514 | jermar | 198 | if (esr.received_illegal_vector) |
1 | jermar | 199 | printf("Received Illegal Vector\n"); |
514 | jermar | 200 | if (esr.illegal_register_address) |
1 | jermar | 201 | printf("Illegal Register Address\n"); |
125 | jermar | 202 | |
514 | jermar | 203 | return !esr.err_bitmap; |
1 | jermar | 204 | } |
205 | |||
514 | jermar | 206 | /** Send all CPUs excluding CPU IPI vector. |
207 | * |
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208 | * @param vector Interrupt vector to be sent. |
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209 | * |
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210 | * @return 0 on failure, 1 on success. |
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5 | jermar | 211 | */ |
212 | int l_apic_broadcast_custom_ipi(__u8 vector) |
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213 | { |
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513 | jermar | 214 | icr_t icr; |
5 | jermar | 215 | |
513 | jermar | 216 | icr.lo = l_apic[ICRlo]; |
217 | icr.delmod = DELMOD_FIXED; |
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218 | icr.destmod = DESTMOD_LOGIC; |
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219 | icr.level = LEVEL_ASSERT; |
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220 | icr.shorthand = SHORTHAND_ALL_EXCL; |
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221 | icr.trigger_mode = TRIGMOD_LEVEL; |
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222 | icr.vector = vector; |
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5 | jermar | 223 | |
513 | jermar | 224 | l_apic[ICRlo] = icr.lo; |
5 | jermar | 225 | |
513 | jermar | 226 | icr.lo = l_apic[ICRlo]; |
515 | jermar | 227 | if (icr.delivs == DELIVS_PENDING) |
5 | jermar | 228 | printf("IPI is pending.\n"); |
229 | |||
230 | return apic_poll_errors(); |
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231 | } |
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232 | |||
514 | jermar | 233 | /** Universal Start-up Algorithm for bringing up the AP processors. |
234 | * |
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235 | * @param apicid APIC ID of the processor to be brought up. |
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236 | * |
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237 | * @return 0 on failure, 1 on success. |
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1 | jermar | 238 | */ |
239 | int l_apic_send_init_ipi(__u8 apicid) |
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240 | { |
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513 | jermar | 241 | icr_t icr; |
1 | jermar | 242 | int i; |
243 | |||
244 | /* |
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245 | * Read the ICR register in and zero all non-reserved fields. |
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246 | */ |
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513 | jermar | 247 | icr.lo = l_apic[ICRlo]; |
248 | icr.hi = l_apic[ICRhi]; |
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1 | jermar | 249 | |
513 | jermar | 250 | icr.delmod = DELMOD_INIT; |
251 | icr.destmod = DESTMOD_PHYS; |
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252 | icr.level = LEVEL_ASSERT; |
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253 | icr.trigger_mode = TRIGMOD_LEVEL; |
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254 | icr.shorthand = SHORTHAND_NONE; |
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255 | icr.vector = 0; |
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256 | icr.dest = apicid; |
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1 | jermar | 257 | |
513 | jermar | 258 | l_apic[ICRhi] = icr.hi; |
259 | l_apic[ICRlo] = icr.lo; |
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27 | jermar | 260 | |
1 | jermar | 261 | /* |
262 | * According to MP Specification, 20us should be enough to |
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263 | * deliver the IPI. |
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264 | */ |
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265 | delay(20); |
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266 | |||
267 | if (!apic_poll_errors()) return 0; |
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268 | |||
513 | jermar | 269 | icr.lo = l_apic[ICRlo]; |
515 | jermar | 270 | if (icr.delivs == DELIVS_PENDING) |
1 | jermar | 271 | printf("IPI is pending.\n"); |
27 | jermar | 272 | |
513 | jermar | 273 | icr.delmod = DELMOD_INIT; |
274 | icr.destmod = DESTMOD_PHYS; |
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275 | icr.level = LEVEL_DEASSERT; |
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276 | icr.shorthand = SHORTHAND_NONE; |
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277 | icr.trigger_mode = TRIGMOD_LEVEL; |
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278 | icr.vector = 0; |
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279 | l_apic[ICRlo] = icr.lo; |
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1 | jermar | 280 | |
281 | /* |
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282 | * Wait 10ms as MP Specification specifies. |
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283 | */ |
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284 | delay(10000); |
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285 | |||
27 | jermar | 286 | if (!is_82489DX_apic(l_apic[LAVR])) { |
287 | /* |
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288 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
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289 | */ |
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290 | for (i = 0; i<2; i++) { |
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513 | jermar | 291 | icr.lo = l_apic[ICRlo]; |
292 | icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */ |
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293 | icr.delmod = DELMOD_STARTUP; |
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294 | icr.destmod = DESTMOD_PHYS; |
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295 | icr.level = LEVEL_ASSERT; |
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296 | icr.shorthand = SHORTHAND_NONE; |
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297 | icr.trigger_mode = TRIGMOD_LEVEL; |
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298 | l_apic[ICRlo] = icr.lo; |
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27 | jermar | 299 | delay(200); |
300 | } |
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1 | jermar | 301 | } |
302 | |||
303 | return apic_poll_errors(); |
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304 | } |
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305 | |||
514 | jermar | 306 | /** Initialize Local APIC. */ |
1 | jermar | 307 | void l_apic_init(void) |
308 | { |
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513 | jermar | 309 | lvt_error_t error; |
310 | lvt_lint_t lint; |
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750 | jermar | 311 | tpr_t tpr; |
513 | jermar | 312 | svr_t svr; |
514 | jermar | 313 | icr_t icr; |
314 | tdcr_t tdcr; |
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513 | jermar | 315 | lvt_tm_t tm; |
672 | jermar | 316 | ldr_t ldr; |
317 | dfr_t dfr; |
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513 | jermar | 318 | __u32 t1, t2; |
1 | jermar | 319 | |
513 | jermar | 320 | /* Initialize LVT Error register. */ |
321 | error.value = l_apic[LVT_Err]; |
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322 | error.masked = true; |
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323 | l_apic[LVT_Err] = error.value; |
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1 | jermar | 324 | |
513 | jermar | 325 | /* Initialize LVT LINT0 register. */ |
326 | lint.value = l_apic[LVT_LINT0]; |
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327 | lint.masked = true; |
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328 | l_apic[LVT_LINT0] = lint.value; |
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1 | jermar | 329 | |
513 | jermar | 330 | /* Initialize LVT LINT1 register. */ |
331 | lint.value = l_apic[LVT_LINT1]; |
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332 | lint.masked = true; |
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333 | l_apic[LVT_LINT1] = lint.value; |
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750 | jermar | 334 | |
335 | /* Task Priority Register initialization. */ |
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336 | tpr.value = l_apic[TPR]; |
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337 | tpr.pri_sc = 0; |
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338 | tpr.pri = 0; |
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339 | l_apic[TPR] = tpr.value; |
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513 | jermar | 340 | |
341 | /* Spurious-Interrupt Vector Register initialization. */ |
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342 | svr.value = l_apic[SVR]; |
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343 | svr.vector = VECTOR_APIC_SPUR; |
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344 | svr.lapic_enabled = true; |
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750 | jermar | 345 | svr.focus_checking = true; |
513 | jermar | 346 | l_apic[SVR] = svr.value; |
347 | |||
31 | jermar | 348 | if (CPU->arch.family >= 6) |
349 | enable_l_apic_in_msr(); |
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1 | jermar | 350 | |
513 | jermar | 351 | /* Interrupt Command Register initialization. */ |
352 | icr.lo = l_apic[ICRlo]; |
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353 | icr.delmod = DELMOD_INIT; |
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354 | icr.destmod = DESTMOD_PHYS; |
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355 | icr.level = LEVEL_DEASSERT; |
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356 | icr.shorthand = SHORTHAND_ALL_INCL; |
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357 | icr.trigger_mode = TRIGMOD_LEVEL; |
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358 | l_apic[ICRlo] = icr.lo; |
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1 | jermar | 359 | |
514 | jermar | 360 | /* Timer Divide Configuration Register initialization. */ |
361 | tdcr.value = l_apic[TDCR]; |
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362 | tdcr.div_value = DIVIDE_1; |
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363 | l_apic[TDCR] = tdcr.value; |
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1 | jermar | 364 | |
514 | jermar | 365 | /* Program local timer. */ |
513 | jermar | 366 | tm.value = l_apic[LVT_Tm]; |
367 | tm.vector = VECTOR_CLK; |
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368 | tm.mode = TIMER_PERIODIC; |
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369 | tm.masked = false; |
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370 | l_apic[LVT_Tm] = tm.value; |
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371 | |||
514 | jermar | 372 | /* Measure and configure the timer to generate timer interrupt each ms. */ |
1 | jermar | 373 | t1 = l_apic[CCRT]; |
374 | l_apic[ICRT] = 0xffffffff; |
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375 | |||
376 | while (l_apic[CCRT] == t1) |
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377 | ; |
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378 | |||
379 | t1 = l_apic[CCRT]; |
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380 | delay(1000); |
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381 | t2 = l_apic[CCRT]; |
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382 | |||
383 | l_apic[ICRT] = t1-t2; |
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672 | jermar | 384 | |
385 | /* Program Logical Destination Register. */ |
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386 | ldr.value = l_apic[LDR]; |
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387 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
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388 | ldr.id = (1<<CPU->id); |
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389 | l_apic[LDR] = ldr.value; |
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390 | |||
391 | /* Program Destination Format Register for Flat mode. */ |
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392 | dfr.value = l_apic[DFR]; |
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393 | dfr.model = MODEL_FLAT; |
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394 | l_apic[DFR] = dfr.value; |
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1 | jermar | 395 | } |
396 | |||
514 | jermar | 397 | /** Local APIC End of Interrupt. */ |
1 | jermar | 398 | void l_apic_eoi(void) |
399 | { |
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400 | l_apic[EOI] = 0; |
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401 | } |
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402 | |||
514 | jermar | 403 | /** Dump content of Local APIC registers. */ |
1 | jermar | 404 | void l_apic_debug(void) |
405 | { |
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406 | #ifdef LAPIC_VERBOSE |
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514 | jermar | 407 | lvt_tm_t tm; |
408 | lvt_lint_t lint; |
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409 | lvt_error_t error; |
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410 | |||
16 | jermar | 411 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
1 | jermar | 412 | |
514 | jermar | 413 | tm.value = l_apic[LVT_Tm]; |
414 | printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
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415 | lint.value = l_apic[LVT_LINT0]; |
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416 | printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
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417 | lint.value = l_apic[LVT_LINT1]; |
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418 | printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
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419 | error.value = l_apic[LVT_Err]; |
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420 | printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
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1 | jermar | 421 | #endif |
422 | } |
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423 | |||
514 | jermar | 424 | /** Local APIC Timer Interrupt. |
425 | * |
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426 | * @param n Interrupt vector number. |
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427 | * @param stack Interrupted stack. |
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428 | */ |
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576 | palkovsky | 429 | void l_apic_timer_interrupt(int n, void *stack) |
1 | jermar | 430 | { |
431 | l_apic_eoi(); |
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432 | clock(); |
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433 | } |
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434 | |||
514 | jermar | 435 | /** Get Local APIC ID. |
436 | * |
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437 | * @return Local APIC ID. |
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438 | */ |
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81 | jermar | 439 | __u8 l_apic_id(void) |
16 | jermar | 440 | { |
515 | jermar | 441 | l_apic_id_t idreg; |
514 | jermar | 442 | |
515 | jermar | 443 | idreg.value = l_apic[L_APIC_ID]; |
444 | return idreg.apic_id; |
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16 | jermar | 445 | } |
446 | |||
514 | jermar | 447 | /** Read from IO APIC register. |
448 | * |
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449 | * @param address IO APIC register address. |
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450 | * |
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451 | * @return Content of the addressed IO APIC register. |
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452 | */ |
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1 | jermar | 453 | __u32 io_apic_read(__u8 address) |
454 | { |
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514 | jermar | 455 | io_regsel_t regsel; |
1 | jermar | 456 | |
514 | jermar | 457 | regsel.value = io_apic[IOREGSEL]; |
458 | regsel.reg_addr = address; |
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459 | io_apic[IOREGSEL] = regsel.value; |
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1 | jermar | 460 | return io_apic[IOWIN]; |
461 | } |
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462 | |||
514 | jermar | 463 | /** Write to IO APIC register. |
464 | * |
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465 | * @param address IO APIC register address. |
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466 | * @param Content to be written to the addressed IO APIC register. |
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467 | */ |
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1 | jermar | 468 | void io_apic_write(__u8 address, __u32 x) |
469 | { |
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514 | jermar | 470 | io_regsel_t regsel; |
471 | |||
472 | regsel.value = io_apic[IOREGSEL]; |
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473 | regsel.reg_addr = address; |
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474 | io_apic[IOREGSEL] = regsel.value; |
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1 | jermar | 475 | io_apic[IOWIN] = x; |
476 | } |
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477 | |||
514 | jermar | 478 | /** Change some attributes of one item in I/O Redirection Table. |
479 | * |
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480 | * @param pin IO APIC pin number. |
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481 | * @param dest Interrupt destination address. |
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482 | * @param v Interrupt vector to trigger. |
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483 | * @param flags Flags. |
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484 | */ |
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485 | void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags) |
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1 | jermar | 486 | { |
512 | jermar | 487 | io_redirection_reg_t reg; |
514 | jermar | 488 | int dlvr = DELMOD_FIXED; |
1 | jermar | 489 | |
490 | if (flags & LOPRI) |
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512 | jermar | 491 | dlvr = DELMOD_LOWPRI; |
492 | |||
514 | jermar | 493 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
494 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
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1 | jermar | 495 | |
672 | jermar | 496 | reg.dest = dest; |
512 | jermar | 497 | reg.destmod = DESTMOD_LOGIC; |
498 | reg.trigger_mode = TRIGMOD_EDGE; |
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499 | reg.intpol = POLARITY_HIGH; |
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500 | reg.delmod = dlvr; |
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501 | reg.intvec = v; |
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1 | jermar | 502 | |
514 | jermar | 503 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
504 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
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1 | jermar | 505 | } |
506 | |||
514 | jermar | 507 | /** Mask IRQs in IO APIC. |
508 | * |
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509 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
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510 | */ |
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1 | jermar | 511 | void io_apic_disable_irqs(__u16 irqmask) |
512 | { |
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512 | jermar | 513 | io_redirection_reg_t reg; |
514 | int i, pin; |
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1 | jermar | 515 | |
516 | for (i=0;i<16;i++) { |
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515 | jermar | 517 | if (irqmask & (1<<i)) { |
1 | jermar | 518 | /* |
519 | * Mask the signal input in IO APIC if there is a |
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520 | * mapping for the respective IRQ number. |
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521 | */ |
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512 | jermar | 522 | pin = smp_irq_to_pin(i); |
1 | jermar | 523 | if (pin != -1) { |
512 | jermar | 524 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
525 | reg.masked = true; |
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526 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
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1 | jermar | 527 | } |
528 | |||
529 | } |
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530 | } |
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531 | } |
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532 | |||
514 | jermar | 533 | /** Unmask IRQs in IO APIC. |
534 | * |
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535 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
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536 | */ |
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1 | jermar | 537 | void io_apic_enable_irqs(__u16 irqmask) |
538 | { |
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512 | jermar | 539 | int i, pin; |
540 | io_redirection_reg_t reg; |
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1 | jermar | 541 | |
542 | for (i=0;i<16;i++) { |
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515 | jermar | 543 | if (irqmask & (1<<i)) { |
1 | jermar | 544 | /* |
545 | * Unmask the signal input in IO APIC if there is a |
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546 | * mapping for the respective IRQ number. |
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547 | */ |
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512 | jermar | 548 | pin = smp_irq_to_pin(i); |
1 | jermar | 549 | if (pin != -1) { |
512 | jermar | 550 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
551 | reg.masked = false; |
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552 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
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1 | jermar | 553 | } |
554 | |||
555 | } |
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556 | } |
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557 | } |
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558 | |||
458 | decky | 559 | #endif /* CONFIG_SMP */ |