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| Rev | Author | Line No. | Line |
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| 1 | jermar | 1 | # |
| 2 | # Copyright (C) 2001-2004 Jakub Jermar |
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| 3 | # All rights reserved. |
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| 4 | # |
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| 5 | # Redistribution and use in source and binary forms, with or without |
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| 6 | # modification, are permitted provided that the following conditions |
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| 7 | # are met: |
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| 8 | # |
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| 9 | # - Redistributions of source code must retain the above copyright |
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| 10 | # notice, this list of conditions and the following disclaimer. |
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| 11 | # - Redistributions in binary form must reproduce the above copyright |
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| 12 | # notice, this list of conditions and the following disclaimer in the |
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| 13 | # documentation and/or other materials provided with the distribution. |
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| 14 | # - The name of the author may not be used to endorse or promote products |
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| 15 | # derived from this software without specific prior written permission. |
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| 16 | # |
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | # |
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| 28 | |||
| 29 | .text |
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| 30 | |||
| 31 | .global atomic_inc |
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| 32 | atomic_inc: |
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| 33 | pushl %ebx |
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| 34 | movl 8(%esp),%ebx |
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| 35 | lock incl (%ebx) |
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| 36 | popl %ebx |
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| 37 | ret |
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| 38 | |||
| 39 | .global atomic_dec |
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| 40 | atomic_dec: |
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| 41 | pushl %ebx |
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| 42 | movl 8(%esp),%ebx |
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| 43 | lock decl (%ebx) |
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| 44 | popl %ebx |
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| 45 | ret |
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| 46 | |||
| 47 | |||
| 48 | #ifdef __SMP__ |
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| 49 | |||
| 50 | |||
| 51 | .global test_and_set |
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| 52 | .global spinlock_arch |
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| 53 | |||
| 54 | test_and_set: |
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| 55 | pushl %ebx |
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| 56 | |||
| 57 | movl 8(%esp),%ebx |
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| 58 | movl $1,%eax |
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| 59 | xchgl %eax,(%ebx) # xchg implicitly turns on the LOCK signal |
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| 60 | |||
| 61 | popl %ebx |
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| 62 | ret |
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| 63 | |||
| 64 | |||
| 65 | # |
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| 66 | # This is a bus-and-hyperthreading-friendly implementation of spinlock |
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| 67 | # |
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| 68 | spinlock_arch: |
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| 69 | pushl %eax |
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| 70 | pushl %ebx |
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| 71 | |||
| 72 | movl 12(%esp),%ebx |
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| 73 | |||
| 74 | 0: |
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| 75 | #ifdef __HT__ |
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| 76 | pause # Pentium 4's with HT love this instruction |
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| 77 | #endif |
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| 78 | movl (%ebx),%eax |
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| 79 | testl %eax,%eax |
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| 80 | jnz 0b # lightweight looping while it is locked |
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| 81 | incl %eax |
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| 82 | xchgl %eax,(%ebx) # now use the atomic operation |
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| 83 | testl %eax,%eax |
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| 84 | jnz 0b |
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| 85 | |||
| 86 | popl %ebx |
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| 87 | popl %eax |
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| 88 | ret |
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| 89 | |||
| 90 | #endif |