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1 jermar 1
/*
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 * Copyright (C) 2001-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __APIC_H__
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#define __APIC_H__
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#include <arch/types.h>
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#include <cpu.h>
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#define FIXED		(0<<0)
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#define LOPRI		(1<<0)
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515 jermar 38
#define APIC_ID_COUNT	16
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1 jermar 40
/* local APIC macros */
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#define IPI_INIT 	0
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#define IPI_STARTUP	0
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513 jermar 44
/** Delivery modes. */
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#define DELMOD_FIXED	0x0
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#define DELMOD_LOWPRI	0x1
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#define DELMOD_SMI	0x2
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/* 0x3 reserved */
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#define DELMOD_NMI	0x4
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#define DELMOD_INIT	0x5
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#define DELMOD_STARTUP	0x6
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#define DELMOD_EXTINT	0x7
1 jermar 53
 
513 jermar 54
/** Destination modes. */
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#define DESTMOD_PHYS	0x0
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#define DESTMOD_LOGIC	0x1
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/** Trigger Modes. */
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#define TRIGMOD_EDGE	0x0
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#define TRIGMOD_LEVEL	0x1
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/** Levels. */
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#define LEVEL_DEASSERT	0x0
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#define LEVEL_ASSERT	0x1
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/** Destination Shorthands. */
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#define SHORTHAND_NONE		0x0
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#define SHORTHAND_SELF		0x1
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#define SHORTHAND_ALL_INCL	0x2
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#define SHORTHAND_ALL_EXCL	0x3
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/** Interrupt Input Pin Polarities. */
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#define POLARITY_HIGH	0x0
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#define POLARITY_LOW	0x1
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514 jermar 76
/** Divide Values. (Bit 2 is always 0) */
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#define DIVIDE_2	0x0
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#define DIVIDE_4	0x1
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#define DIVIDE_8	0x2
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#define DIVIDE_16	0x3
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#define DIVIDE_32	0x8
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#define DIVIDE_64	0x9
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#define DIVIDE_128	0xa
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#define DIVIDE_1	0xb
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/** Timer Modes. */
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#define TIMER_ONESHOT	0x0
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#define TIMER_PERIODIC	0x1
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515 jermar 90
/** Delivery status. */
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#define DELIVS_IDLE	0x0
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#define DELIVS_PENDING	0x1
1 jermar 93
 
515 jermar 94
/** Destination masks. */
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#define DEST_ALL	0xff
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672 jermar 97
/** Dest format models. */
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#define MODEL_FLAT	0xf
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#define MODEL_CLUSTER	0x0
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513 jermar 101
/** Interrupt Command Register. */
1 jermar 102
#define ICRlo		(0x300/sizeof(__u32))
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#define ICRhi		(0x310/sizeof(__u32))
513 jermar 104
struct icr {
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	union {
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		__u32 lo;
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		struct {
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			__u8 vector;			/**< Interrupt Vector. */
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			unsigned delmod : 3;		/**< Delivery Mode. */
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			unsigned destmod : 1;		/**< Destination Mode. */
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			unsigned delivs : 1;		/**< Delivery status (RO). */
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			unsigned : 1;			/**< Reserved. */
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			unsigned level : 1;		/**< Level. */
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			unsigned trigger_mode : 1;	/**< Trigger Mode. */
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			unsigned : 2;			/**< Reserved. */
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			unsigned shorthand : 2;		/**< Destination Shorthand. */
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			unsigned : 12;			/**< Reserved. */
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		} __attribute__ ((packed));
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	};
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	union {
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		__u32 hi;
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		struct {
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			unsigned : 24;			/**< Reserved. */
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			__u8 dest;			/**< Destination field. */
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		} __attribute__ ((packed));
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	};
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} __attribute__ ((packed));
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typedef struct icr icr_t;
1 jermar 129
 
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/* End Of Interrupt */
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#define EOI		(0x0b0/sizeof(__u32))
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514 jermar 133
/** Error Status Register. */
1 jermar 134
#define ESR		(0x280/sizeof(__u32))
514 jermar 135
union esr {
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	__u32 value;
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	__u8 err_bitmap;
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	struct {
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		unsigned send_checksum_error : 1;
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		unsigned receive_checksum_error : 1;
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		unsigned send_accept_error : 1;
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		unsigned receive_accept_error : 1;
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		unsigned : 1;
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		unsigned send_illegal_vector : 1;
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		unsigned received_illegal_vector : 1;
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		unsigned illegal_register_address : 1;
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		unsigned : 24;
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	} __attribute__ ((packed));
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};
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typedef union esr esr_t;
1 jermar 151
 
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/* Task Priority Register */
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#define TPR		(0x080/sizeof(__u32))
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#define TPRClear	0xffffff00
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513 jermar 156
/** Spurious-Interrupt Vector Register. */
1 jermar 157
#define SVR		(0x0f0/sizeof(__u32))
513 jermar 158
union svr {
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	__u32 value;
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	struct {
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		__u8 vector;			/**< Spurious Vector */
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		unsigned lapic_enabled : 1;	/**< APIC Software Enable/Disable */
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		unsigned focus_checking : 1;	/**< Focus Processor Checking */
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		unsigned : 22;			/**< Reserved. */
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	} __attribute__ ((packed));
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};
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typedef union svr svr_t;
1 jermar 168
 
514 jermar 169
/** Time Divide Configuration Register. */
1 jermar 170
#define TDCR		(0x3e0/sizeof(__u32))
514 jermar 171
union tdcr {
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	__u32 value;
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	struct {
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		unsigned div_value : 4;		/**< Divide Value, bit 2 is always 0. */
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		unsigned : 28;			/**< Reserved. */
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	} __attribute__ ((packed));
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};
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typedef union tdcr tdcr_t;
1 jermar 179
 
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/* Initial Count Register for Timer */
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#define ICRT		(0x380/sizeof(__u32))
182
 
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/* Current Count Register for Timer */
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#define CCRT		(0x390/sizeof(__u32))
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513 jermar 186
/** LVT Timer register. */
1 jermar 187
#define LVT_Tm		(0x320/sizeof(__u32))
513 jermar 188
union lvt_tm {
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	__u32 value;
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	struct {
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		__u8 vector;		/**< Local Timer Interrupt vector. */
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		unsigned : 4;		/**< Reserved. */
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		unsigned delivs : 1;	/**< Delivery status (RO). */
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		unsigned : 3;		/**< Reserved. */
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		unsigned masked : 1;	/**< Interrupt Mask. */
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		unsigned mode : 1;	/**< Timer Mode. */
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		unsigned : 14;		/**< Reserved. */
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	} __attribute__ ((packed));
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};
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typedef union lvt_tm lvt_tm_t;
201
 
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/** LVT LINT registers. */
1 jermar 203
#define LVT_LINT0	(0x350/sizeof(__u32))
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#define LVT_LINT1	(0x360/sizeof(__u32))
513 jermar 205
union lvt_lint {
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	__u32 value;
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	struct {
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		__u8 vector;			/**< LINT Interrupt vector. */
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		unsigned delmod : 3;		/**< Delivery Mode. */
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		unsigned : 1;			/**< Reserved. */
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		unsigned delivs : 1;		/**< Delivery status (RO). */
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		unsigned intpol : 1;		/**< Interrupt Input Pin Polarity. */
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		unsigned irr : 1;		/**< Remote IRR (RO). */
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		unsigned trigger_mode : 1;	/**< Trigger Mode. */
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		unsigned masked : 1;		/**< Interrupt Mask. */
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		unsigned : 15;			/**< Reserved. */
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	} __attribute__ ((packed));
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};
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typedef union lvt_lint lvt_lint_t;
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/** LVT Error register. */
1 jermar 222
#define LVT_Err		(0x370/sizeof(__u32))
513 jermar 223
union lvt_error {
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	__u32 value;
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	struct {
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		__u8 vector;		/**< Local Timer Interrupt vector. */
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		unsigned : 4;		/**< Reserved. */
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		unsigned delivs : 1;	/**< Delivery status (RO). */
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		unsigned : 3;		/**< Reserved. */
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		unsigned masked : 1;	/**< Interrupt Mask. */
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		unsigned : 15;		/**< Reserved. */
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	} __attribute__ ((packed));
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};
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typedef union lvt_error lvt_error_t;
235
 
514 jermar 236
/** Local APIC ID Register. */
1 jermar 237
#define L_APIC_ID	(0x020/sizeof(__u32))
515 jermar 238
union l_apic_id {
514 jermar 239
	__u32 value;
240
	struct {
241
		unsigned : 24;		/**< Reserved. */
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		__u8 apic_id;		/**< Local APIC ID. */
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	} __attribute__ ((packed));
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};
515 jermar 245
typedef union l_apic_id l_apic_id_t;
1 jermar 246
 
27 jermar 247
/* Local APIC Version Register */
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#define LAVR		(0x030/sizeof(__u32))
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#define LAVR_Mask	0xff
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#define is_local_apic(x)	(((x)&LAVR_Mask&0xf0)==0x1)
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#define is_82489DX_apic(x)	((((x)&LAVR_Mask&0xf0)==0x0))
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#define is_local_xapic(x)	(((x)&LAVR_Mask)==0x14)
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672 jermar 254
/** Logical Destination Register. */
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#define  LDR		(0x0d0/sizeof(__u32))
256
union ldr {
257
	__u32 value;
258
	struct {
259
		unsigned : 24;		/**< Reserver. */
260
		__u8 id;		/**< Logical APIC ID. */
261
	} __attribute__ ((packed));
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};
263
typedef union ldr ldr_t;
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265
/** Destination Format Register. */
266
#define DFR		(0x0e0/sizeof(__u32))
267
union dfr {
268
	__u32 value;
269
	struct {
270
		unsigned : 28;		/**< Reserved, all ones. */
271
		unsigned model : 4;	/**< Model. */
272
	} __attribute__ ((packed));
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};
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typedef union dfr dfr_t;
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1 jermar 276
/* IO APIC */
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#define IOREGSEL	(0x00/sizeof(__u32))
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#define IOWIN		(0x10/sizeof(__u32))
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#define IOAPICID	0x00
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#define IOAPICVER	0x01
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#define IOAPICARB	0x02
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#define IOREDTBL	0x10
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514 jermar 285
/** I/O Register Select Register. */
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union io_regsel {
287
	__u32 value;
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	struct {
289
		__u8 reg_addr;		/**< APIC Register Address. */
290
		unsigned : 24;		/**< Reserved. */
291
	} __attribute__ ((packed));
292
};
293
typedef union io_regsel io_regsel_t;
294
 
512 jermar 295
/** I/O Redirection Register. */
296
struct io_redirection_reg {
297
	union {
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		__u32 lo;
299
		struct {
513 jermar 300
			__u8 intvec;			/**< Interrupt Vector. */
512 jermar 301
			unsigned delmod : 3;		/**< Delivery Mode. */
302
			unsigned destmod : 1; 		/**< Destination mode. */
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			unsigned delivs : 1;		/**< Delivery status (RO). */
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			unsigned intpol : 1;		/**< Interrupt Input Pin Polarity. */
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			unsigned irr : 1;		/**< Remote IRR (RO). */
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			unsigned trigger_mode : 1;	/**< Trigger Mode. */
307
			unsigned masked : 1;		/**< Interrupt Mask. */
308
			unsigned : 15;			/**< Reserved. */
513 jermar 309
		} __attribute__ ((packed));
512 jermar 310
	};
311
	union {
312
		__u32 hi;
313
		struct {
314
			unsigned : 24;			/**< Reserved. */
513 jermar 315
			__u8 dest : 8;		/**< Destination Field. */
316
		} __attribute__ ((packed));
512 jermar 317
	};
318
 
319
} __attribute__ ((packed));
320
typedef struct io_redirection_reg io_redirection_reg_t;
321
 
515 jermar 322
 
323
/** IO APIC Identification Register. */
324
union io_apic_id {
325
	__u32 value;
326
	struct {
327
		unsigned : 24;		/**< Reserved. */
328
		unsigned apic_id : 4;	/**< IO APIC ID. */
329
		unsigned : 4;		/**< Reserved. */
330
	} __attribute__ ((packed));
331
};
332
typedef union io_apic_id io_apic_id_t;
333
 
1 jermar 334
extern volatile __u32 *l_apic;
335
extern volatile __u32 *io_apic;
336
 
337
extern __u32 apic_id_mask;
338
 
339
extern void apic_init(void);
340
 
341
extern void l_apic_init(void);
342
extern void l_apic_eoi(void);
5 jermar 343
extern int l_apic_broadcast_custom_ipi(__u8 vector);
1 jermar 344
extern int l_apic_send_init_ipi(__u8 apicid);
345
extern void l_apic_debug(void);
81 jermar 346
extern __u8 l_apic_id(void);
1 jermar 347
 
348
extern __u32 io_apic_read(__u8 address);
349
extern void io_apic_write(__u8 address , __u32 x);
514 jermar 350
extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags);
1 jermar 351
extern void io_apic_disable_irqs(__u16 irqmask);
352
extern void io_apic_enable_irqs(__u16 irqmask);
353
 
354
#endif