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| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | #ifndef __APIC_H__ |
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| 30 | #define __APIC_H__ |
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| 31 | |||
| 32 | #include <arch/types.h> |
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| 33 | #include <cpu.h> |
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| 34 | |||
| 35 | #define FIXED (0<<0) |
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| 36 | #define LOPRI (1<<0) |
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| 37 | |||
| 38 | /* local APIC macros */ |
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| 39 | #define IPI_INIT 0 |
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| 40 | #define IPI_STARTUP 0 |
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| 41 | |||
| 513 | jermar | 42 | /** Delivery modes. */ |
| 43 | #define DELMOD_FIXED 0x0 |
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| 44 | #define DELMOD_LOWPRI 0x1 |
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| 45 | #define DELMOD_SMI 0x2 |
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| 46 | /* 0x3 reserved */ |
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| 47 | #define DELMOD_NMI 0x4 |
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| 48 | #define DELMOD_INIT 0x5 |
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| 49 | #define DELMOD_STARTUP 0x6 |
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| 50 | #define DELMOD_EXTINT 0x7 |
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| 1 | jermar | 51 | |
| 513 | jermar | 52 | /** Destination modes. */ |
| 53 | #define DESTMOD_PHYS 0x0 |
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| 54 | #define DESTMOD_LOGIC 0x1 |
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| 55 | |||
| 56 | /** Trigger Modes. */ |
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| 57 | #define TRIGMOD_EDGE 0x0 |
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| 58 | #define TRIGMOD_LEVEL 0x1 |
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| 59 | |||
| 60 | /** Levels. */ |
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| 61 | #define LEVEL_DEASSERT 0x0 |
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| 62 | #define LEVEL_ASSERT 0x1 |
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| 63 | |||
| 64 | /** Destination Shorthands. */ |
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| 65 | #define SHORTHAND_NONE 0x0 |
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| 66 | #define SHORTHAND_SELF 0x1 |
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| 67 | #define SHORTHAND_ALL_INCL 0x2 |
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| 68 | #define SHORTHAND_ALL_EXCL 0x3 |
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| 69 | |||
| 70 | /** Interrupt Input Pin Polarities. */ |
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| 71 | #define POLARITY_HIGH 0x0 |
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| 72 | #define POLARITY_LOW 0x1 |
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| 73 | |||
| 1 | jermar | 74 | #define SEND_PENDING (1<<12) |
| 75 | |||
| 513 | jermar | 76 | /** Interrupt Command Register. */ |
| 1 | jermar | 77 | #define ICRlo (0x300/sizeof(__u32)) |
| 78 | #define ICRhi (0x310/sizeof(__u32)) |
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| 513 | jermar | 79 | struct icr { |
| 80 | union { |
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| 81 | __u32 lo; |
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| 82 | struct { |
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| 83 | __u8 vector; /**< Interrupt Vector. */ |
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| 84 | unsigned delmod : 3; /**< Delivery Mode. */ |
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| 85 | unsigned destmod : 1; /**< Destination Mode. */ |
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| 86 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 87 | unsigned : 1; /**< Reserved. */ |
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| 88 | unsigned level : 1; /**< Level. */ |
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| 89 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 90 | unsigned : 2; /**< Reserved. */ |
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| 91 | unsigned shorthand : 2; /**< Destination Shorthand. */ |
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| 92 | unsigned : 12; /**< Reserved. */ |
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| 93 | } __attribute__ ((packed)); |
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| 94 | }; |
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| 95 | union { |
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| 96 | __u32 hi; |
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| 97 | struct { |
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| 98 | unsigned : 24; /**< Reserved. */ |
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| 99 | __u8 dest; /**< Destination field. */ |
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| 100 | } __attribute__ ((packed)); |
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| 101 | }; |
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| 102 | } __attribute__ ((packed)); |
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| 103 | typedef struct icr icr_t; |
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| 1 | jermar | 104 | |
| 105 | /* End Of Interrupt */ |
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| 106 | #define EOI (0x0b0/sizeof(__u32)) |
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| 107 | |||
| 108 | /* Error Status Register */ |
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| 109 | #define ESR (0x280/sizeof(__u32)) |
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| 110 | #define ESRClear ((0xffffff<<8)|(1<<4)) |
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| 111 | |||
| 112 | /* Task Priority Register */ |
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| 113 | #define TPR (0x080/sizeof(__u32)) |
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| 114 | #define TPRClear 0xffffff00 |
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| 115 | |||
| 513 | jermar | 116 | /** Spurious-Interrupt Vector Register. */ |
| 1 | jermar | 117 | #define SVR (0x0f0/sizeof(__u32)) |
| 513 | jermar | 118 | union svr { |
| 119 | __u32 value; |
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| 120 | struct { |
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| 121 | __u8 vector; /**< Spurious Vector */ |
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| 122 | unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable */ |
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| 123 | unsigned focus_checking : 1; /**< Focus Processor Checking */ |
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| 124 | unsigned : 22; /**< Reserved. */ |
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| 125 | } __attribute__ ((packed)); |
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| 126 | }; |
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| 127 | typedef union svr svr_t; |
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| 1 | jermar | 128 | |
| 513 | jermar | 129 | /* Time Divide Configuration Register */ |
| 1 | jermar | 130 | #define TDCR (0x3e0/sizeof(__u32)) |
| 131 | #define TDCRClear (~0xb) |
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| 132 | |||
| 133 | /* Initial Count Register for Timer */ |
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| 134 | #define ICRT (0x380/sizeof(__u32)) |
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| 135 | |||
| 136 | /* Current Count Register for Timer */ |
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| 137 | #define CCRT (0x390/sizeof(__u32)) |
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| 138 | |||
| 513 | jermar | 139 | /** Timer Modes. */ |
| 140 | #define TIMER_ONESHOT 0x0 |
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| 141 | #define TIMER_PERIODIC 0x1 |
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| 142 | |||
| 143 | /** LVT Timer register. */ |
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| 1 | jermar | 144 | #define LVT_Tm (0x320/sizeof(__u32)) |
| 513 | jermar | 145 | union lvt_tm { |
| 146 | __u32 value; |
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| 147 | struct { |
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| 148 | __u8 vector; /**< Local Timer Interrupt vector. */ |
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| 149 | unsigned : 4; /**< Reserved. */ |
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| 150 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 151 | unsigned : 3; /**< Reserved. */ |
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| 152 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 153 | unsigned mode : 1; /**< Timer Mode. */ |
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| 154 | unsigned : 14; /**< Reserved. */ |
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| 155 | } __attribute__ ((packed)); |
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| 156 | }; |
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| 157 | typedef union lvt_tm lvt_tm_t; |
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| 158 | |||
| 159 | /** LVT LINT registers. */ |
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| 1 | jermar | 160 | #define LVT_LINT0 (0x350/sizeof(__u32)) |
| 161 | #define LVT_LINT1 (0x360/sizeof(__u32)) |
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| 513 | jermar | 162 | union lvt_lint { |
| 163 | __u32 value; |
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| 164 | struct { |
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| 165 | __u8 vector; /**< LINT Interrupt vector. */ |
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| 166 | unsigned delmod : 3; /**< Delivery Mode. */ |
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| 167 | unsigned : 1; /**< Reserved. */ |
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| 168 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 169 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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| 170 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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| 171 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 172 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 173 | unsigned : 15; /**< Reserved. */ |
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| 174 | } __attribute__ ((packed)); |
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| 175 | }; |
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| 176 | typedef union lvt_lint lvt_lint_t; |
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| 177 | |||
| 178 | /** LVT Error register. */ |
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| 1 | jermar | 179 | #define LVT_Err (0x370/sizeof(__u32)) |
| 513 | jermar | 180 | union lvt_error { |
| 181 | __u32 value; |
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| 182 | struct { |
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| 183 | __u8 vector; /**< Local Timer Interrupt vector. */ |
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| 184 | unsigned : 4; /**< Reserved. */ |
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| 185 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 186 | unsigned : 3; /**< Reserved. */ |
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| 187 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 188 | unsigned : 15; /**< Reserved. */ |
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| 189 | } __attribute__ ((packed)); |
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| 190 | }; |
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| 191 | typedef union lvt_error lvt_error_t; |
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| 192 | |||
| 193 | |||
| 1 | jermar | 194 | #define LVT_PCINT (0x340/sizeof(__u32)) |
| 195 | |||
| 196 | /* Local APIC ID Register */ |
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| 197 | #define L_APIC_ID (0x020/sizeof(__u32)) |
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| 198 | #define L_APIC_IDClear (~(0xf<<24)) |
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| 16 | jermar | 199 | #define L_APIC_IDShift 24 |
| 200 | #define L_APIC_IDMask 0xf |
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| 1 | jermar | 201 | |
| 27 | jermar | 202 | /* Local APIC Version Register */ |
| 203 | #define LAVR (0x030/sizeof(__u32)) |
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| 204 | #define LAVR_Mask 0xff |
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| 205 | #define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1) |
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| 206 | #define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0)) |
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| 207 | #define is_local_xapic(x) (((x)&LAVR_Mask)==0x14) |
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| 208 | |||
| 1 | jermar | 209 | /* IO APIC */ |
| 210 | #define IOREGSEL (0x00/sizeof(__u32)) |
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| 211 | #define IOWIN (0x10/sizeof(__u32)) |
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| 212 | |||
| 213 | #define IOAPICID 0x00 |
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| 214 | #define IOAPICVER 0x01 |
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| 215 | #define IOAPICARB 0x02 |
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| 216 | #define IOREDTBL 0x10 |
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| 217 | |||
| 512 | jermar | 218 | /** I/O Redirection Register. */ |
| 219 | struct io_redirection_reg { |
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| 220 | union { |
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| 221 | __u32 lo; |
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| 222 | struct { |
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| 513 | jermar | 223 | __u8 intvec; /**< Interrupt Vector. */ |
| 512 | jermar | 224 | unsigned delmod : 3; /**< Delivery Mode. */ |
| 225 | unsigned destmod : 1; /**< Destination mode. */ |
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| 226 | unsigned delivs : 1; /**< Delivery status (RO). */ |
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| 227 | unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */ |
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| 228 | unsigned irr : 1; /**< Remote IRR (RO). */ |
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| 229 | unsigned trigger_mode : 1; /**< Trigger Mode. */ |
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| 230 | unsigned masked : 1; /**< Interrupt Mask. */ |
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| 231 | unsigned : 15; /**< Reserved. */ |
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| 513 | jermar | 232 | } __attribute__ ((packed)); |
| 512 | jermar | 233 | }; |
| 234 | union { |
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| 235 | __u32 hi; |
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| 236 | struct { |
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| 237 | unsigned : 24; /**< Reserved. */ |
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| 513 | jermar | 238 | __u8 dest : 8; /**< Destination Field. */ |
| 239 | } __attribute__ ((packed)); |
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| 512 | jermar | 240 | }; |
| 241 | |||
| 242 | } __attribute__ ((packed)); |
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| 243 | |||
| 244 | typedef struct io_redirection_reg io_redirection_reg_t; |
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| 245 | |||
| 1 | jermar | 246 | extern volatile __u32 *l_apic; |
| 247 | extern volatile __u32 *io_apic; |
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| 248 | |||
| 249 | extern __u32 apic_id_mask; |
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| 250 | |||
| 251 | extern void apic_init(void); |
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| 268 | palkovsky | 252 | extern void apic_spurious(__u8 n, __native stack[]); |
| 1 | jermar | 253 | |
| 254 | extern void l_apic_init(void); |
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| 255 | extern void l_apic_eoi(void); |
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| 5 | jermar | 256 | extern int l_apic_broadcast_custom_ipi(__u8 vector); |
| 1 | jermar | 257 | extern int l_apic_send_init_ipi(__u8 apicid); |
| 258 | extern void l_apic_debug(void); |
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| 268 | palkovsky | 259 | extern void l_apic_timer_interrupt(__u8 n, __native stack[]); |
| 81 | jermar | 260 | extern __u8 l_apic_id(void); |
| 1 | jermar | 261 | |
| 262 | extern __u32 io_apic_read(__u8 address); |
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| 263 | extern void io_apic_write(__u8 address , __u32 x); |
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| 264 | extern void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags); |
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| 265 | extern void io_apic_disable_irqs(__u16 irqmask); |
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| 266 | extern void io_apic_enable_irqs(__u16 irqmask); |
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| 267 | |||
| 268 | #endif |