Rev 1100 | Rev 1697 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
||
| 3 | * All rights reserved. |
||
| 4 | * |
||
| 5 | * Redistribution and use in source and binary forms, with or without |
||
| 6 | * modification, are permitted provided that the following conditions |
||
| 7 | * are met: |
||
| 8 | * |
||
| 9 | * - Redistributions of source code must retain the above copyright |
||
| 10 | * notice, this list of conditions and the following disclaimer. |
||
| 11 | * - Redistributions in binary form must reproduce the above copyright |
||
| 12 | * notice, this list of conditions and the following disclaimer in the |
||
| 13 | * documentation and/or other materials provided with the distribution. |
||
| 14 | * - The name of the author may not be used to endorse or promote products |
||
| 15 | * derived from this software without specific prior written permission. |
||
| 16 | * |
||
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
||
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
||
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
||
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
||
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
||
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
| 27 | */ |
||
| 28 | |||
| 11 | jermar | 29 | #ifndef __ia32_ATOMIC_H__ |
| 30 | #define __ia32_ATOMIC_H__ |
||
| 1 | jermar | 31 | |
| 32 | #include <arch/types.h> |
||
| 1100 | palkovsky | 33 | #include <arch/barrier.h> |
| 34 | #include <preemption.h> |
||
| 1104 | jermar | 35 | #include <typedefs.h> |
| 1 | jermar | 36 | |
| 475 | jermar | 37 | static inline void atomic_inc(atomic_t *val) { |
| 458 | decky | 38 | #ifdef CONFIG_SMP |
| 625 | palkovsky | 39 | __asm__ volatile ("lock incl %0\n" : "=m" (val->count)); |
| 115 | jermar | 40 | #else |
| 625 | palkovsky | 41 | __asm__ volatile ("incl %0\n" : "=m" (val->count)); |
| 458 | decky | 42 | #endif /* CONFIG_SMP */ |
| 115 | jermar | 43 | } |
| 1 | jermar | 44 | |
| 475 | jermar | 45 | static inline void atomic_dec(atomic_t *val) { |
| 458 | decky | 46 | #ifdef CONFIG_SMP |
| 625 | palkovsky | 47 | __asm__ volatile ("lock decl %0\n" : "=m" (val->count)); |
| 115 | jermar | 48 | #else |
| 625 | palkovsky | 49 | __asm__ volatile ("decl %0\n" : "=m" (val->count)); |
| 458 | decky | 50 | #endif /* CONFIG_SMP */ |
| 115 | jermar | 51 | } |
| 52 | |||
| 1104 | jermar | 53 | static inline long atomic_postinc(atomic_t *val) |
| 477 | vana | 54 | { |
| 1104 | jermar | 55 | long r; |
| 627 | jermar | 56 | |
| 477 | vana | 57 | __asm__ volatile ( |
| 557 | jermar | 58 | "movl $1, %0\n" |
| 59 | "lock xaddl %0, %1\n" |
||
| 627 | jermar | 60 | : "=r" (r), "=m" (val->count) |
| 477 | vana | 61 | ); |
| 627 | jermar | 62 | |
| 477 | vana | 63 | return r; |
| 64 | } |
||
| 65 | |||
| 1104 | jermar | 66 | static inline long atomic_postdec(atomic_t *val) |
| 477 | vana | 67 | { |
| 1104 | jermar | 68 | long r; |
| 627 | jermar | 69 | |
| 477 | vana | 70 | __asm__ volatile ( |
| 557 | jermar | 71 | "movl $-1, %0\n" |
| 72 | "lock xaddl %0, %1\n" |
||
| 631 | palkovsky | 73 | : "=r" (r), "=m" (val->count) |
| 477 | vana | 74 | ); |
| 627 | jermar | 75 | |
| 477 | vana | 76 | return r; |
| 77 | } |
||
| 78 | |||
| 1024 | jermar | 79 | #define atomic_preinc(val) (atomic_postinc(val)+1) |
| 80 | #define atomic_predec(val) (atomic_postdec(val)-1) |
||
| 477 | vana | 81 | |
| 633 | palkovsky | 82 | static inline __u32 test_and_set(atomic_t *val) { |
| 83 | __u32 v; |
||
| 115 | jermar | 84 | |
| 85 | __asm__ volatile ( |
||
| 86 | "movl $1, %0\n" |
||
| 259 | palkovsky | 87 | "xchgl %0, %1\n" |
| 625 | palkovsky | 88 | : "=r" (v),"=m" (val->count) |
| 115 | jermar | 89 | ); |
| 90 | |||
| 91 | return v; |
||
| 92 | } |
||
| 93 | |||
| 1104 | jermar | 94 | /** ia32 specific fast spinlock */ |
| 1100 | palkovsky | 95 | static inline void atomic_lock_arch(atomic_t *val) |
| 96 | { |
||
| 97 | __u32 tmp; |
||
| 115 | jermar | 98 | |
| 1100 | palkovsky | 99 | preemption_disable(); |
| 100 | __asm__ volatile ( |
||
| 101 | "0:;" |
||
| 102 | #ifdef CONFIG_HT |
||
| 103 | "pause;" /* Pentium 4's HT love this instruction */ |
||
| 104 | #endif |
||
| 105 | "mov %0, %1;" |
||
| 106 | "testl %1, %1;" |
||
| 1104 | jermar | 107 | "jnz 0b;" /* Lightweight looping on locked spinlock */ |
| 1100 | palkovsky | 108 | |
| 109 | "incl %1;" /* now use the atomic operation */ |
||
| 110 | "xchgl %0, %1;" |
||
| 111 | "testl %1, %1;" |
||
| 112 | "jnz 0b;" |
||
| 113 | : "=m"(val->count),"=r"(tmp) |
||
| 114 | ); |
||
| 115 | /* |
||
| 116 | * Prevent critical section code from bleeding out this way up. |
||
| 117 | */ |
||
| 118 | CS_ENTER_BARRIER(); |
||
| 119 | } |
||
| 1 | jermar | 120 | |
| 121 | #endif |