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1 jermar 1
/*
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 * Copyright (C) 2001-2004 Jakub Jermar
393 bondari 3
 * Copyright (C) 2005 Sergey Bondari
1 jermar 4
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __ia32_ASM_H__
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#define __ia32_ASM_H__
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#include <arch/pm.h>
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#include <arch/types.h>
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#include <config.h>
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extern __u32 interrupt_handler_size;
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extern void paging_on(void);
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extern void interrupt_handlers(void);
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extern void enable_l_apic_in_msr(void);
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extern void asm_delay_loop(__u32 t);
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extern void asm_fake_loop(__u32 t);
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/** Halt CPU
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 *
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 * Halt the current CPU until interrupt event.
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 */
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static inline void cpu_halt(void) { __asm__("hlt\n"); };
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static inline void cpu_sleep(void) { __asm__("hlt\n"); };
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1074 palkovsky 57
#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
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    { \
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    __native res; \
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    __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
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    return res; \
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    }
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
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    { \
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    __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
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    }
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GEN_READ_REG(cr0);
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GEN_READ_REG(cr2);
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GEN_READ_REG(cr3);
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GEN_WRITE_REG(cr3);
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GEN_READ_REG(dr0);
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GEN_READ_REG(dr1);
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GEN_READ_REG(dr2);
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GEN_READ_REG(dr3);
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GEN_READ_REG(dr6);
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GEN_READ_REG(dr7);
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GEN_WRITE_REG(dr0);
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GEN_WRITE_REG(dr1);
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GEN_WRITE_REG(dr2);
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GEN_WRITE_REG(dr3);
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GEN_WRITE_REG(dr6);
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GEN_WRITE_REG(dr7);
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352 bondari 88
/** Byte to port
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 *
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 * Output byte to port
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 *
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 * @param port Port to write to
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 * @param val Value to write
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 */
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static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
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/** Word to port
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 *
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 * Output word to port
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 *
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 * @param port Port to write to
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 * @param val Value to write
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 */
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static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
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/** Double word to port
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 *
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 * Output double word to port
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 *
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 * @param port Port to write to
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 * @param val Value to write
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 */
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static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
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/** Byte from port
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 *
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 * Get byte from port
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 *
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 * @param port Port to read from
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 * @return Value read
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 */
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static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Word from port
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 *
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 * Get word from port
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 *
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 * @param port Port to read from
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 * @return Value read
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 */
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static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Double word from port
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 *
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 * Get double word from port
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 *
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 * @param port Port to read from
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 * @return Value read
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 */
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static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Enable interrupts.
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 *
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 * Enable interrupts and return previous
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 * value of EFLAGS.
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 *
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 * @return Old interrupt priority level.
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 */
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static inline ipl_t interrupts_enable(void)
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{
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    ipl_t v;
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    __asm__ volatile (
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        "pushf\n\t"
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        "popl %0\n\t"
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        "sti\n"
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        : "=r" (v)
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    );
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    return v;
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}
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/** Disable interrupts.
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 *
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 * Disable interrupts and return previous
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 * value of EFLAGS.
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 *
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 * @return Old interrupt priority level.
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 */
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static inline ipl_t interrupts_disable(void)
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{
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    ipl_t v;
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    __asm__ volatile (
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        "pushf\n\t"
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        "popl %0\n\t"
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        "cli\n"
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        : "=r" (v)
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    );
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    return v;
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}
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/** Restore interrupt priority level.
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 *
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 * Restore EFLAGS.
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 *
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 * @param ipl Saved interrupt priority level.
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 */
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static inline void interrupts_restore(ipl_t ipl)
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{
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    __asm__ volatile (
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        "pushl %0\n\t"
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        "popf\n"
413 jermar 191
        : : "r" (ipl)
115 jermar 192
    );
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}
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413 jermar 195
/** Return interrupt priority level.
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 *
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 * @return EFLAFS.
115 jermar 198
 */
432 jermar 199
static inline ipl_t interrupts_read(void)
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{
413 jermar 201
    ipl_t v;
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    __asm__ volatile (
358 bondari 203
        "pushf\n\t"
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        "popl %0\n"
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        : "=r" (v)
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    );
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    return v;
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}
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173 jermar 210
/** Return base address of current stack
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 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE bytes long.
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 * The stack must start on page boundary.
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 */
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static inline __address get_stack_base(void)
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{
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    __address v;
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    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
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    return v;
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}
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348 jermar 225
static inline __u64 rdtsc(void)
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{
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    __u64 v;
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    __asm__ volatile("rdtsc\n" : "=A" (v));
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    return v;
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}
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581 palkovsky 234
/** Return current IP address */
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static inline __address * get_ip()
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{
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    __address *ip;
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239
    __asm__ volatile (
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        "mov %%eip, %0"
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        : "=r" (ip)
242
        );
243
    return ip;
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}
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597 jermar 246
/** Invalidate TLB Entry.
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 *
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 * @param addr Address on a page whose TLB entry is to be invalidated.
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 */
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static inline void invlpg(__address addr)
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{
984 palkovsky 252
    __asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr));
597 jermar 253
}
254
 
1186 jermar 255
/** Load GDTR register from memory.
256
 *
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 * @param gdtr_reg Address of memory from where to load GDTR.
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 */
1187 jermar 259
static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
1186 jermar 260
{
1251 jermar 261
    __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
1186 jermar 262
}
263
 
264
/** Store GDTR register to memory.
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 *
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 * @param gdtr_reg Address of memory to where to load GDTR.
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 */
1187 jermar 268
static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
1186 jermar 269
{
1251 jermar 270
    __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
1186 jermar 271
}
272
 
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/** Load IDTR register from memory.
274
 *
275
 * @param idtr_reg Address of memory from where to load IDTR.
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 */
1187 jermar 277
static inline void idtr_load(ptr_16_32_t *idtr_reg)
1186 jermar 278
{
1251 jermar 279
    __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg));
1186 jermar 280
}
281
 
282
/** Load TR from descriptor table.
283
 *
284
 * @param sel Selector specifying descriptor of TSS segment.
285
 */
286
static inline void tr_load(__u16 sel)
287
{
288
    __asm__ volatile ("ltr %0" : : "r" (sel));
289
}
290
 
1 jermar 291
#endif