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/*
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 * Copyright (C) 2001-2004 Jakub Jermar
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 * Copyright (C) 2005-2006 Ondrej Palkovsky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <arch/pm.h>
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#include <arch/mm/page.h>
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#include <arch/types.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <interrupt.h>
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#include <mm/as.h>
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#include <config.h>
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#include <memstr.h>
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#include <mm/slab.h>
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#include <debug.h>
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/*
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 * There is no segmentation in long mode so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 */
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descriptor_t gdt[GDT_ITEMS] = {
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    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 1,
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      .special     = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* KDATA descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* UDATA descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 1,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* UTEXT descriptor */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_USER,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 1,
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      .special     = 0,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* KTEXT 32-bit protected, for protected mode before long mode */
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    { .limit_0_15  = 0xffff,
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      .base_0_15   = 0,
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      .base_16_23  = 0,
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      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
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      .limit_16_19 = 0xf,
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      .available   = 0,
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      .longmode    = 0,
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      .special     = 1,
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      .granularity = 1,
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      .base_24_31  = 0 },
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    /* TSS descriptor - set up will be completed later,
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     * on AMD64 it is 64-bit - 2 items in table */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* VESA Init descriptor */
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#ifdef CONFIG_FB    
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    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
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#endif
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};
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idescriptor_t idt[IDT_ITEMS];
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ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
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ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
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static tss_t tss;
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tss_t *tss_p = NULL;
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void gdt_tss_setbase(descriptor_t *d, __address base)
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{
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    tss_descriptor_t *td = (tss_descriptor_t *) d;
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    td->base_0_15 = base & 0xffff;
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    td->base_16_23 = ((base) >> 16) & 0xff;
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    td->base_24_31 = ((base) >> 24) & 0xff;
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    td->base_32_63 = ((base) >> 32);
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}
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void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
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{
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    struct tss_descriptor *td = (tss_descriptor_t *) d;
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    td->limit_0_15 = limit & 0xffff;
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    td->limit_16_19 = (limit >> 16) & 0xf;
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}
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void idt_setoffset(idescriptor_t *d, __address offset)
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{
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    /*
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     * Offset is a linear address.
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     */
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    d->offset_0_15 = offset & 0xffff;
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    d->offset_16_31 = offset >> 16 & 0xffff;
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    d->offset_32_63 = offset >> 32;
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}
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void tss_initialize(tss_t *t)
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{
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    memsetb((__address) t, sizeof(tss_t), 0);
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}
158
 
159
/*
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 * This function takes care of proper setup of IDT and IDTR.
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 */
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void idt_init(void)
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{
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    idescriptor_t *d;
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    int i;
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167
    for (i = 0; i < IDT_ITEMS; i++) {
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        d = &idt[i];
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        d->unused = 0;
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        d->selector = gdtselector(KTEXT_DES);
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        d->present = 1;
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        d->type = AR_INTERRUPT; /* masking interrupt */
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        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
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        exc_register(i, "undef", (iroutine)null_interrupt);
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    }
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    exc_register( 7, "nm_fault", nm_fault);
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    exc_register(12, "ss_fault", ss_fault);
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    exc_register(13, "gp_fault", gp_fault);
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    exc_register(14, "ident_mapper", ident_page_fault);
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}
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/** Initialize segmentation - code/data/idt tables
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 *
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 */
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void pm_init(void)
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{
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    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
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    tss_descriptor_t *tss_desc;
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    /*
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     * Each CPU has its private GDT and TSS.
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     * All CPUs share one IDT.
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     */
198
 
199
    if (config.cpu_active == 1) {
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        idt_init();
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        /*
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         * NOTE: bootstrap CPU has statically allocated TSS, because
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         * the heap hasn't been initialized so far.
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         */
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        tss_p = &tss;
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    }
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    else {
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        /* We are going to use malloc, which may return
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         * non boot-mapped pointer, initialize the CR3 register
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         * ahead of page_init */
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        write_cr3((__address) AS_KERNEL->page_table);
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        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
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        if (!tss_p)
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            panic("could not allocate TSS\n");
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    }
217
 
218
    tss_initialize(tss_p);
219
 
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    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
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    tss_desc->present = 1;
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    tss_desc->type = AR_TSS;
223
    tss_desc->dpl = PL_KERNEL;
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225
    gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
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    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
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1186 jermar 228
    gdtr_load(&gdtr);
229
    idtr_load(&idtr);
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    /*
231
     * As of this moment, the current CPU has its own GDT pointing
232
     * to its own TSS. We just need to load the TR register.
233
     */
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    tr_load(gdtselector(TSS_DES));
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}