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173 jermar 1
/*
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#ifndef __amd64_ASM_H__
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#define __amd64_ASM_H__
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#include <arch/pm.h>
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#include <arch/types.h>
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#include <config.h>
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597 jermar 36
extern void asm_delay_loop(__u32 t);
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extern void asm_fake_loop(__u32 t);
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/** Return base address of current stack.
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 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE bytes long.
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 * The stack must start on page boundary.
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 */
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static inline __address get_stack_base(void)
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{
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    __address v;
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    __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
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    return v;
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}
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348 jermar 54
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
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static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
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/** Byte from port
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 *
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 * Get byte from port
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 *
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 * @param port Port to read from
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 * @return Value read
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 */
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static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
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/** Byte to port
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 *
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 * Output byte to port
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 *
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 * @param port Port to write to
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 * @param val Value to write
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 */
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static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
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806 palkovsky 76
/** Swap Hidden part of GS register with visible one */
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static inline void swapgs(void) { __asm__ volatile("swapgs"); }
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413 jermar 79
/** Enable interrupts.
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 *
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 * Enable interrupts and return previous
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 * value of EFLAGS.
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 *
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 * @return Old interrupt priority level.
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 */
413 jermar 86
static inline ipl_t interrupts_enable(void) {
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    ipl_t v;
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    __asm__ volatile (
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        "pushfq\n"
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        "popq %0\n"
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        "sti\n"
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        : "=r" (v)
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    );
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    return v;
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}
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413 jermar 97
/** Disable interrupts.
200 palkovsky 98
 *
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 * Disable interrupts and return previous
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 * value of EFLAGS.
413 jermar 101
 *
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 * @return Old interrupt priority level.
200 palkovsky 103
 */
413 jermar 104
static inline ipl_t interrupts_disable(void) {
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    ipl_t v;
200 palkovsky 106
    __asm__ volatile (
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        "pushfq\n"
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        "popq %0\n"
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        "cli\n"
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        : "=r" (v)
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        );
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    return v;
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}
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413 jermar 115
/** Restore interrupt priority level.
200 palkovsky 116
 *
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 * Restore EFLAGS.
413 jermar 118
 *
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 * @param ipl Saved interrupt priority level.
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 */
413 jermar 121
static inline void interrupts_restore(ipl_t ipl) {
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    __asm__ volatile (
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        "pushq %0\n"
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        "popfq\n"
413 jermar 125
        : : "r" (ipl)
200 palkovsky 126
        );
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}
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413 jermar 129
/** Return interrupt priority level.
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 *
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 * Return EFLAFS.
413 jermar 132
 *
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 * @return Current interrupt priority level.
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 */
413 jermar 135
static inline ipl_t interrupts_read(void) {
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    ipl_t v;
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    __asm__ volatile (
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        "pushfq\n"
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        "popq %0\n"
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        : "=r" (v)
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    );
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    return v;
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}
200 palkovsky 144
 
803 palkovsky 145
/** Write to MSR */
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static inline void write_msr(__u32 msr, __u64 value)
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{
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    __asm__ volatile (
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        "wrmsr;" : : "c" (msr),
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        "a" ((__u32)(value)),
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        "d" ((__u32)(value >> 32))
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        );
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}
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803 palkovsky 155
static inline __native read_msr(__u32 msr)
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{
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    __u32 ax, dx;
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    __asm__ volatile (
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        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
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        );
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    return ((__u64)dx << 32) | ax;
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}
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/** Enable local APIC
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 *
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 * Enable local APIC in MSR.
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 */
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static inline void enable_l_apic_in_msr()
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{
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    __asm__ volatile (
348 jermar 173
        "movl $0x1b, %%ecx\n"
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        "rdmsr\n"
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        "orl $(1<<11),%%eax\n"
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        "orl $(0xfee00000),%%eax\n"
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        "wrmsr\n"
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        :
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        :
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        :"%eax","%ecx","%edx"
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        );
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}
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581 palkovsky 184
static inline __address * get_ip()
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{
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    __address *ip;
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188
    __asm__ volatile (
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        "mov %%rip, %0"
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        : "=r" (ip)
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        );
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    return ip;
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}
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597 jermar 195
/** Invalidate TLB Entry.
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 *
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 * @param addr Address on a page whose TLB entry is to be invalidated.
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 */
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static inline void invlpg(__address addr)
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{
1186 jermar 201
    __asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr)));
597 jermar 202
}
581 palkovsky 203
 
1186 jermar 204
/** Load GDTR register from memory.
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 *
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 * @param gdtr_reg Address of memory from where to load GDTR.
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 */
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static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
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{
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    __asm__ volatile ("lgdt %0\n" : : "m" (*gdtr_reg));
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}
212
 
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/** Store GDTR register to memory.
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 *
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 * @param gdtr_reg Address of memory to where to load GDTR.
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 */
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static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
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{
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    __asm__ volatile ("sgdt %0\n" : : "m" (*gdtr_reg));
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}
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/** Load IDTR register from memory.
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 *
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 * @param idtr_reg Address of memory from where to load IDTR.
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 */
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static inline void idtr_load(struct ptr_16_64 *idtr_reg)
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{
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    __asm__ volatile ("lidt %0\n" : : "m" (*idtr_reg));
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}
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/** Load TR from descriptor table.
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 *
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 * @param sel Selector specifying descriptor of TSS segment.
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 */
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static inline void tr_load(__u16 sel)
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{
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    __asm__ volatile ("ltr %0" : : "r" (sel));
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}
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1072 palkovsky 240
#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
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    { \
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    __native res; \
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    __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
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    return res; \
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    }
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#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
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    { \
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    __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
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    }
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GEN_READ_REG(cr0);
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GEN_READ_REG(cr2);
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GEN_READ_REG(cr3);
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GEN_WRITE_REG(cr3);
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GEN_READ_REG(dr0);
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GEN_READ_REG(dr1);
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GEN_READ_REG(dr2);
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GEN_READ_REG(dr3);
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GEN_READ_REG(dr6);
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GEN_READ_REG(dr7);
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GEN_WRITE_REG(dr0);
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GEN_WRITE_REG(dr1);
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GEN_WRITE_REG(dr2);
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GEN_WRITE_REG(dr3);
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GEN_WRITE_REG(dr6);
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GEN_WRITE_REG(dr7);
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271
 
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extern size_t interrupt_handler_size;
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extern void interrupt_handlers(void);
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173 jermar 275
#endif