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122 | jermar | 1 | <?xml version="1.0" encoding="UTF-8"?> |
126 | jermar | 2 | <appendix id="archspecs"> |
130 | palkovsky | 3 | <?dbhtml filename="arch.html"?> |
4 | |||
122 | jermar | 5 | <title>Architecture specific notes</title> |
6 | |||
7 | <section> |
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130 | palkovsky | 8 | <title>AMD64/Intel EM64T</title> |
122 | jermar | 9 | |
130 | palkovsky | 10 | <para>The AMD64 architecture is a 64-bit extension of the older IA-32 |
11 | architecture. Only 64-bit applications are supported. Creating this port |
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12 | was relatively easy, because it shares a lot of common code with IA-32 |
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13 | platform. However, the 64-bit extension has some specifics, which made the |
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14 | porting interesting.</para> |
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15 | |||
16 | <section> |
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17 | <title>Virtual Memory</title> |
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18 | |||
19 | <para>The AMD64 architecture uses standard processor defined 4-level |
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20 | page mapping of 4KB pages. The NX(no-execute) flag on individual pages |
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21 | is fully supported.</para> |
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22 | </section> |
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23 | |||
24 | <section> |
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25 | <title>TLB-only Paging</title> |
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26 | |||
27 | <para>All memory on the AMD64 architecture is memory mapped, if the |
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28 | kernel needs to access physical memory, a mapping must be created. |
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29 | During boot process the boot loader creates mapping for the first 20MB |
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30 | of physical memory. To correctly initialize the page mapping system, an |
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31 | identity mapping of whole physical memory must be created. However, to |
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32 | create the mapping it is unavoidable to allocate new - possibly unmapped |
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33 | - frames from frame allocator. The ia32 solves it by mapping first 2GB |
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34 | memory during boot process. The same solution on 64-bit platform becomes |
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35 | unfeasible because of the size of the possible address space.</para> |
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36 | |||
37 | <para>As soon as the exception routines are initialized, a special page |
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38 | fault exception handler is installed which provides a complete view of |
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39 | physical memory until the real page mapping system is initialized. It |
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40 | dynamically changes the page tables to always contain exactly the |
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41 | faulting address. The page then becomes cached in the TLB and on the |
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42 | next page fault the same tables can be utilized to handle another |
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43 | mapping.</para> |
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44 | </section> |
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45 | |||
46 | <section> |
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47 | <title>Mapping of Physical Memory</title> |
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48 | |||
49 | <para>The AMD64 ABI document describes several modes of program layout. |
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50 | The operating system kernel should be compiled in a |
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51 | <emphasis>kernel</emphasis> mode - the kernel is located in the negative |
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52 | 2 gigabytes (0xffffffff80000000-0xfffffffffffffffff) and can access data |
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53 | anywhere in the 64-bit space. This wouldn't allow kernel to see directly |
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54 | more than 2GB of physical memory. HelenOS duplicates the virtual mapping |
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55 | of the physical memory starting at 0xffff800000000000 and accesses all |
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56 | external references using this address range.</para> |
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57 | </section> |
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58 | |||
59 | <section> |
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60 | <title>Thread Local Storage</title> |
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61 | |||
62 | <para>The code accessing thread local storage uses a segment register FS |
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63 | as a base. The thread local storage is stored in the hidden 64-bit part |
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64 | of the FS register which must be written using priviledged machine |
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65 | specific instructions. Special syscall to change this register is |
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66 | provided to user applications. The TLS address for this platform is |
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67 | expected to point just after the end of the thread local data.</para> |
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68 | </section> |
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69 | |||
70 | <section> |
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71 | <title>Fast SYSCALL/SYSRET Support</title> |
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72 | |||
73 | <para>The entry point for system calls was traditionally a speed problem |
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74 | on IA32 architecture. AMD64 supports a SYSCALL/SYSRET instructions. Upon |
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75 | encountering SYSCALL instruction, the processor changes privilege mode |
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76 | and transfers control to an address stored in machine specific register. |
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77 | Unlike other similar instructions it does not change stack to a known |
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78 | kernel stack, which must be done by the syscall entry routine. A hidden |
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79 | part of a GS register is provided to support the entry routine with data |
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80 | needed for switching to kernel stack.</para> |
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81 | </section> |
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82 | |||
83 | <section> |
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84 | <title>Debugging Support</title> |
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85 | |||
86 | <para>To provide developers tools for finding bugs, hardware breakpoints |
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87 | and watchpoints are supported. The kernel also supports self-debugging - |
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88 | it sets watchpoints on certain data and upon every modification |
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89 | automatically checks whether a correct value was written. It is |
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90 | worthwhile to mention, that since this feature was implemented, the |
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91 | watchpoint was never fired.</para> |
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92 | </section> |
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122 | jermar | 93 | </section> |
130 | palkovsky | 94 | |
95 | <section> |
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96 | <title>Intel IA32</title> |
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97 | |||
98 | <para>The IA32 architecture uses 4K pages and processor supported 2-level |
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99 | page tables. Along with AMD64 It is one of the 2 architectures that fully |
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100 | supports SMP configurations. IA32 is mostly similar to AMD64, it even |
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101 | shares a lot of code. The debugging support is the same as with AMD64. The |
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102 | thread local storage uses GS register.</para> |
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103 | </section> |
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104 | |||
105 | <section> |
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106 | <title>MIPS32</title> |
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107 | |||
108 | <para>Both little and big endian kernels are supported. In order to test |
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109 | different page size it was set to 16K. The MIPS architecture is TLB-only, |
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110 | the kernel simulates 2-level page tables. On processors that support it, |
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111 | lazy FPU context switching is implemented.</para> |
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112 | |||
113 | <section> |
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114 | <title>Thread Local Storage</title> |
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115 | |||
116 | <para>The thread local storage support in compilers is a relatively |
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117 | recent phenomena. The standardization of such support for MIPS platform |
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118 | is very new and even the newest versions of GCC cannot generate 100% |
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119 | correct code. Because of some weird MIPS processor variants, it was |
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120 | decided, that the TLS pointer will be gathered not from some of the free |
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121 | registers, but a special instruction was devised and the kernel is |
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122 | supposed to emulate it. HelenOS expects that the TLS pointer is in the |
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123 | K1 register. Upon encountering the reserved instruction exception and |
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124 | checking that the application is requesting a TLS pointer, it returns |
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125 | the contents of the K1 register. The K1 register is expected to point |
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126 | 0x7000 bytes after the beginning of the thread local data.</para> |
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127 | </section> |
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128 | </section> |
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129 | |||
130 | <section> |
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131 | <title>Power PC</title> |
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132 | |||
133 | <para></para> |
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134 | </section> |
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135 | |||
136 | <section> |
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137 | <title>IA-64</title> |
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138 | |||
139 | <para></para> |
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140 | </section> |
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122 | jermar | 141 | </appendix> |