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1281 palkovsky 1
/*
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 * Copyright (C) 2006 Ondrej Palkovsky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1284 palkovsky 29
/** IRQ notification framework
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 *
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 * This framework allows applications to register to receive a notification
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 * when interrupt is detected. The application may provide a simple 'top-half'
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 * handler as part of its registration, which can perform simple operations
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 * (read/write port/memory, add information to notification ipc message).
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 *
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 * The structure of a notification message is as follows:
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 * - METHOD: IPC_M_INTERRUPT
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 * - ARG1: interrupt number
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 * - ARG2: payload modified by a 'top-half' handler
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 * - ARG3: interrupt counter (may be needed to assure correct order
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 *         in multithreaded drivers)
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 */
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1281 palkovsky 44
#include <arch.h>
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#include <mm/slab.h>
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#include <errno.h>
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#include <ipc/ipc.h>
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#include <ipc/irq.h>
1284 palkovsky 49
#include <atomic.h>
1281 palkovsky 50
 
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typedef struct {
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    SPINLOCK_DECLARE(lock);
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    answerbox_t *box;
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    irq_code_t *code;
1284 palkovsky 55
    atomic_t counter;
1281 palkovsky 56
} ipc_irq_t;
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static ipc_irq_t *irq_conns = NULL;
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static int irq_conns_size;
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#include <print.h>
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/* Execute code associated with IRQ notification */
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static void code_execute(call_t *call, irq_code_t *code)
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{
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    int i;
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    if (!code)
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        return;
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    for (i=0; i < code->cmdcount;i++) {
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        switch (code->cmds[i].cmd) {
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        case CMD_MEM_READ_1:
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            IPC_SET_ARG2(call->data, *((__u8 *)code->cmds[i].addr));
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            break;
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        case CMD_MEM_READ_2:
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            IPC_SET_ARG2(call->data, *((__u16 *)code->cmds[i].addr));
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            break;
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        case CMD_MEM_READ_4:
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            IPC_SET_ARG2(call->data, *((__u32 *)code->cmds[i].addr));
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            break;
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        case CMD_MEM_READ_8:
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            IPC_SET_ARG2(call->data, *((__u64 *)code->cmds[i].addr));
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            break;
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        case CMD_MEM_WRITE_1:
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            *((__u8 *)code->cmds[i].addr) = code->cmds[i].value;
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            break;
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        case CMD_MEM_WRITE_2:
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            *((__u16 *)code->cmds[i].addr) = code->cmds[i].value;
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            break;
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        case CMD_MEM_WRITE_4:
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            *((__u32 *)code->cmds[i].addr) = code->cmds[i].value;
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            break;
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        case CMD_MEM_WRITE_8:
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            *((__u64 *)code->cmds[i].addr) = code->cmds[i].value;
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            break;
1284 palkovsky 97
#if defined(ia32) || defined(amd64)
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        case CMD_PORT_READ_1:
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            IPC_SET_ARG2(call->data, inb((long)code->cmds[i].addr));
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            break;
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        case CMD_PORT_WRITE_1:
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            outb((long)code->cmds[i].addr, code->cmds[i].value);
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            break;
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#endif
1281 palkovsky 105
        default:
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            break;
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        }
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    }
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}
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static void code_free(irq_code_t *code)
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{
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    if (code) {
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        free(code->cmds);
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        free(code);
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    }
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}
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static irq_code_t * code_from_uspace(irq_code_t *ucode)
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{
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    irq_code_t *code;
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    irq_cmd_t *ucmds;
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    code = malloc(sizeof(*code), 0);
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    copy_from_uspace(code, ucode, sizeof(*code));
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127
    if (code->cmdcount > IRQ_MAX_PROG_SIZE) {
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        free(code);
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        return NULL;
130
    }
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    ucmds = code->cmds;
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    code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0);
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    copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount));
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135
    return code;
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}
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138
/** Unregister task from irq */
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void ipc_irq_unregister(answerbox_t *box, int irq)
140
{
141
    ipl_t ipl;
142
 
143
    ipl = interrupts_disable();
144
    spinlock_lock(&irq_conns[irq].lock);
145
    if (irq_conns[irq].box == box) {
146
        irq_conns[irq].box = NULL;
147
        code_free(irq_conns[irq].code);
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        irq_conns[irq].code = NULL;
149
    }
150
 
151
    spinlock_unlock(&irq_conns[irq].lock);
152
    interrupts_restore(ipl);
153
}
154
 
155
/** Register an answerbox as a receiving end of interrupts notifications */
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int ipc_irq_register(answerbox_t *box, int irq, irq_code_t *ucode)
157
{
158
    ipl_t ipl;
159
    irq_code_t *code;
160
 
161
    ASSERT(irq_conns);
162
 
163
    if (ucode) {
164
        code = code_from_uspace(ucode);
165
        if (!code)
166
            return EBADMEM;
167
    } else
168
        code = NULL;
169
 
170
    ipl = interrupts_disable();
171
    spinlock_lock(&irq_conns[irq].lock);
172
 
173
    if (irq_conns[irq].box) {
174
        spinlock_unlock(&irq_conns[irq].lock);
175
        interrupts_restore(ipl);
176
        code_free(code);
177
        return EEXISTS;
178
    }
179
    irq_conns[irq].box = box;
180
    irq_conns[irq].code = code;
1284 palkovsky 181
    atomic_set(&irq_conns[irq].counter, 0);
1281 palkovsky 182
    spinlock_unlock(&irq_conns[irq].lock);
183
    interrupts_restore(ipl);
184
 
185
    return 0;
186
}
187
 
188
/** Notify process that an irq had happend
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 *
190
 * We expect interrupts to be disabled
191
 */
192
void ipc_irq_send_notif(int irq)
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{
194
    call_t *call;
195
 
196
    ASSERT(irq_conns);
197
    spinlock_lock(&irq_conns[irq].lock);
198
 
199
    if (irq_conns[irq].box) {
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        call = ipc_call_alloc(FRAME_ATOMIC);
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        call->flags |= IPC_CALL_NOTIF;
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        IPC_SET_METHOD(call->data, IPC_M_INTERRUPT);
203
        IPC_SET_ARG1(call->data, irq);
1284 palkovsky 204
        IPC_SET_ARG3(call->data, atomic_preinc(&irq_conns[irq].counter));
1281 palkovsky 205
 
206
        /* Execute code to handle irq */
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        code_execute(call, irq_conns[irq].code);
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209
        spinlock_lock(&irq_conns[irq].box->irq_lock);
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        list_append(&call->list, &irq_conns[irq].box->irq_notifs);
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        spinlock_unlock(&irq_conns[irq].box->irq_lock);
212
 
213
        waitq_wakeup(&irq_conns[irq].box->wq, 0);
214
    }
215
 
216
    spinlock_unlock(&irq_conns[irq].lock);
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}
218
 
219
 
220
/** Initialize table of interrupt handlers */
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void ipc_irq_make_table(int irqcount)
222
{
223
    int i;
224
 
225
    irq_conns_size = irqcount;
226
    irq_conns = malloc(irqcount * (sizeof(*irq_conns)), 0);
227
    for (i=0; i < irqcount; i++) {
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        spinlock_initialize(&irq_conns[i].lock, "irq_ipc_lock");
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        irq_conns[i].box = NULL;
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        irq_conns[i].code = NULL;
231
    }
232
}
233
 
234
/** Disconnect all irq's notifications
235
 *
236
 * TODO: It may be better to do some linked list, so that
237
 *       we wouldn't need to go through whole array every cleanup
238
 */
239
void ipc_irq_cleanup(answerbox_t *box)
240
{
241
    int i;
242
    ipl_t ipl;
243
 
244
    for (i=0; i < irq_conns_size; i++) {
245
        ipl = interrupts_disable();
246
        spinlock_lock(&irq_conns[i].lock);
247
        if (irq_conns[i].box == box)
248
            irq_conns[i].box = NULL;
249
        spinlock_unlock(&irq_conns[i].lock);
250
        interrupts_restore(ipl);
251
    }
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}