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1889 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2006 Jakub Jermar |
1889 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup sparc64mm |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
35 | #include <arch/mm/tsb.h> |
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1891 | jermar | 36 | #include <arch/mm/tlb.h> |
2141 | jermar | 37 | #include <arch/mm/page.h> |
1891 | jermar | 38 | #include <arch/barrier.h> |
1889 | jermar | 39 | #include <mm/as.h> |
40 | #include <arch/types.h> |
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1891 | jermar | 41 | #include <macros.h> |
42 | #include <debug.h> |
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1889 | jermar | 43 | |
2141 | jermar | 44 | #define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1) |
1891 | jermar | 45 | |
1889 | jermar | 46 | /** Invalidate portion of TSB. |
47 | * |
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2048 | jermar | 48 | * We assume that the address space is already locked. Note that respective |
49 | * portions of both TSBs are invalidated at a time. |
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1889 | jermar | 50 | * |
51 | * @param as Address space. |
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52 | * @param page First page to invalidate in TSB. |
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2048 | jermar | 53 | * @param pages Number of pages to invalidate. Value of (count_t) -1 means the |
54 | * whole TSB. |
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1889 | jermar | 55 | */ |
56 | void tsb_invalidate(as_t *as, uintptr_t page, count_t pages) |
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57 | { |
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1891 | jermar | 58 | index_t i0, i; |
59 | count_t cnt; |
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60 | |||
61 | ASSERT(as->arch.itsb && as->arch.dtsb); |
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62 | |||
2141 | jermar | 63 | i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; |
64 | cnt = min(pages * MMU_PAGES_PER_PAGE, ITSB_ENTRY_COUNT); |
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1891 | jermar | 65 | |
66 | for (i = 0; i < cnt; i++) { |
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2048 | jermar | 67 | as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid = |
2141 | jermar | 68 | true; |
2048 | jermar | 69 | as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid = |
2141 | jermar | 70 | true; |
1891 | jermar | 71 | } |
1889 | jermar | 72 | } |
73 | |||
1891 | jermar | 74 | /** Copy software PTE to ITSB. |
75 | * |
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2141 | jermar | 76 | * @param t Software PTE. |
77 | * @param index Zero if lower 8K-subpage, one if higher 8K subpage. |
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1891 | jermar | 78 | */ |
2141 | jermar | 79 | void itsb_pte_copy(pte_t *t, index_t index) |
1891 | jermar | 80 | { |
81 | as_t *as; |
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82 | tsb_entry_t *tsb; |
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2141 | jermar | 83 | index_t entry; |
1891 | jermar | 84 | |
85 | as = t->as; |
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2141 | jermar | 86 | entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
87 | tsb = &as->arch.itsb[entry]; |
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1891 | jermar | 88 | |
89 | /* |
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90 | * We use write barriers to make sure that the TSB load |
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91 | * won't use inconsistent data or that the fault will |
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92 | * be repeated. |
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93 | */ |
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94 | |||
1960 | jermar | 95 | tsb->tag.invalid = true; /* invalidate the entry |
96 | * (tag target has this |
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97 | * set to 0) */ |
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1891 | jermar | 98 | |
99 | write_barrier(); |
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100 | |||
101 | tsb->tag.context = as->asid; |
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2141 | jermar | 102 | tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >> |
103 | VA_TAG_PAGE_SHIFT; |
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1891 | jermar | 104 | tsb->data.value = 0; |
105 | tsb->data.size = PAGESIZE_8K; |
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2141 | jermar | 106 | tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
1891 | jermar | 107 | tsb->data.cp = t->c; |
1960 | jermar | 108 | tsb->data.p = t->k; /* p as privileged */ |
1891 | jermar | 109 | tsb->data.v = t->p; |
110 | |||
111 | write_barrier(); |
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112 | |||
1960 | jermar | 113 | tsb->tag.invalid = false; /* mark the entry as valid */ |
1891 | jermar | 114 | } |
115 | |||
116 | /** Copy software PTE to DTSB. |
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117 | * |
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2141 | jermar | 118 | * @param t Software PTE. |
119 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
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120 | * @param ro If true, the mapping is copied read-only. |
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1891 | jermar | 121 | */ |
2141 | jermar | 122 | void dtsb_pte_copy(pte_t *t, index_t index, bool ro) |
1891 | jermar | 123 | { |
124 | as_t *as; |
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125 | tsb_entry_t *tsb; |
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2141 | jermar | 126 | index_t entry; |
1891 | jermar | 127 | |
128 | as = t->as; |
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2141 | jermar | 129 | entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; |
130 | tsb = &as->arch.dtsb[entry]; |
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1891 | jermar | 131 | |
132 | /* |
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133 | * We use write barriers to make sure that the TSB load |
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134 | * won't use inconsistent data or that the fault will |
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135 | * be repeated. |
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136 | */ |
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137 | |||
1960 | jermar | 138 | tsb->tag.invalid = true; /* invalidate the entry |
139 | * (tag target has this |
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140 | * set to 0) */ |
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1891 | jermar | 141 | |
142 | write_barrier(); |
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143 | |||
144 | tsb->tag.context = as->asid; |
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2141 | jermar | 145 | tsb->tag.va_tag = (t->page + (index << MMU_PAGE_WIDTH)) >> |
146 | VA_TAG_PAGE_SHIFT; |
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1891 | jermar | 147 | tsb->data.value = 0; |
148 | tsb->data.size = PAGESIZE_8K; |
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2141 | jermar | 149 | tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; |
1891 | jermar | 150 | tsb->data.cp = t->c; |
2009 | jermar | 151 | #ifdef CONFIG_VIRT_IDX_DCACHE |
1891 | jermar | 152 | tsb->data.cv = t->c; |
2009 | jermar | 153 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
1960 | jermar | 154 | tsb->data.p = t->k; /* p as privileged */ |
1891 | jermar | 155 | tsb->data.w = ro ? false : t->w; |
156 | tsb->data.v = t->p; |
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157 | |||
158 | write_barrier(); |
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159 | |||
1960 | jermar | 160 | tsb->tag.invalid = true; /* mark the entry as valid */ |
1891 | jermar | 161 | } |
162 | |||
1889 | jermar | 163 | /** @} |
164 | */ |